AT32UC3L032-D3UR Atmel, AT32UC3L032-D3UR Datasheet - Page 334

• Manufacturer Part Number: AT32UC3L032-D3UR
• Description: MCU AVR32 32KB FLASH 48TLLGA
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L032-D3UR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TLLGA
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 7
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: AT32UC3L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 9 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

18.7.2
18.7.3
Table 18-2.
32099F–11/2010
Offset
0x00C
0x01C
0x000
0x004
0x008
0x010
0x014
0x018
0x020
0x024
0x028
Configuration Protection
Access Protection
GPIO Register Memory Map
Peripheral Mux Register 0
Peripheral Mux Register 0
Peripheral Mux Register 0
Peripheral Mux Register 0
Peripheral Mux Register 1
Peripheral Mux Register 1
Peripheral Mux Register 1
GPIO Enable Register
GPIO Enable Register
GPIO Enable Register
GPIO Enable Register
Register
ten to one. Again all bits written to zero remain unchanged. Note that for some registers (e.g.
IFR), not all access methods are permitted.
Note that for ports with less than 32 bits, the corresponding control registers will have unused
bits. This is also the case for features that are not implemented for a specific pin. Writing to an
unused bit will have no effect. Reading unused bits will always return 0.
In order to protect the configuration of individual GPIO pins from software failure, configuration
bits for individual GPIO pins may be locked by writing a one to the corresponding bit in the LOCK
register. While this bit is one, any write to the same bit position in any lockable GPIO register
using the Peripheral Bus (PB) will not have an effect. The CPU Local Bus is not checked and
thus allowed to write to all bits in a CPU Local Bus mapped register no mather the LOCK value.
The registers required to clear bits in the LOCK register are protected by the access protection
mechanism described in
software failure.
In order to protect critical registers from software failure, some registers are protected by a key
protection mechanism. These registers can only be changed by first writing the UNLOCK regis-
ter, then the protected register. Protected registers are indicated in
register contains a key field which must always be written to 0xAA, and an OFFSET field corre-
sponding to the offset of the register to be modified.
The next write operation resets the UNLOCK register, so if the register is to be modified again,
the UNLOCK register must be written again.
Attempting to write to a protected register without first writing the UNLOCK register results in the
write operation being discarded, and the Access Error bit in the Access Status Register
(ASR.AE) will be set.
Read/Write
Read/Write
Read/Write
Function
Toggle
Toggle
Clear
Clear
Clear
Set
Set
Set
Section
Register Name
18.7.3, ensuring the LOCK mechanism itself is robust against
GPERS
GPERC
PMR0C
PMR1C
GPERT
PMR0S
PMR0T
PMR1S
GPER
PMR0
PMR1
Read/Write
Read/Write
Read/Write
Write-only
Write-only
Write-only
Write-only
Write-only
Write-only
Write-only
Write-only
Access
AT32UC3L016/32/64
Reset
-
-
-
(1)
(1)
(1)
Table
Protection
Config.
18-2. The UNLOCK
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Protection
Access
N
N
N
N
N
N
N
N
N
N
N
334