AT32UC3L032-D3UR Atmel, AT32UC3L032-D3UR Datasheet - Page 523

• Manufacturer Part Number: AT32UC3L032-D3UR
• Description: MCU AVR32 32KB FLASH 48TLLGA
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L032-D3UR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TLLGA
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 7
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: AT32UC3L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 9 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

• SMBPECERR: SMBus PEC Error
• SMBTOUT: SMBus Timeout
• NAK: NAK Received
• ORUN: Overrun
• URUN: Underrun
• TRA: Transmitter Mode
• TCOMP: Transmission Complete
• SEN: Slave Enabled
• TXRDY: TX Buffer Ready
• RXRDY: RX Buffer Ready
32099F–11/2010
This bit is set when SMBus PEC error has occurred.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when SMBus timeout has occurred.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when NAK was received from master during slave transmitter operation.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when overrun has occurred in slave receiver mode. Can only occur if CR.STREN=0.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when underrun has occurred in slave transmitter mode. Can only occur if CR.STREN=0.
This bit is cleared when the corresponding bit in SCR is written to one.
0: The slave is in slave receiver mode.
1: The slave is in slave transmitter mode.
This bit is set when transmission is complete. Set after receiving a STOP after being addressed.
This bit is cleared when the corresponding bit in SCR is written to one.
0: The slave interface is disabled.
1: The slave interface is enabled.
0: The TX buffer is full and should not be written to.
1: The TX buffer is empty, and can accept new data.
0: No RX data ready in RHR.
1: RX data is ready to be read from RHR.
AT32UC3L016/32/64
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