AT32UC3L032-D3UR Atmel, AT32UC3L032-D3UR Datasheet - Page 793

• Manufacturer Part Number: AT32UC3L032-D3UR
• Description: MCU AVR32 32KB FLASH 48TLLGA
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L032-D3UR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TLLGA
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 7
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: AT32UC3L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 9 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

32.7.3
Table 32-14. Digital Frequency Locked Loop Characteristics
Notes:
32099F–11/2010
Symbol
f
f
I
t
t
OUT
REF
DFLL
STARTUP
LOCK
1. Spread Spectrum Generator (SSG) is disabled by writing a zero to the EN bit in the SCIF.DFLL0SSG register.
2. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
Digital Frequency Locked Loop (DFLL) Characteristics
cess technology. These values are not covered by test limits in production.
Parameter
Output frequency
Reference frequency
FINE resolution
Frequency drift over voltage
and temperature
Accuracy
Power consumption
Startup time
Lock time
(2)
(2)
(2)
(2)
Conditions
FINE > 100, all COARSE values
Fine lock, f
Accurate lock, f
RCSYS/2, SSG disabled
Fine lock, f
disabled
Accurate lock, f
clk RCSYS/2, SSG disabled
Within 90% of final values
f
f
clock = RCSYS/2, SSG disabled
REF
REF
= 32kHz, fine lock, SSG disabled
= 32kHz, accurate lock, dithering
REF
REF
= 8-150kHz, SSG
= 32kHz, SSG disabled
REF
REF
= 32kHz, dither clk
= 8-150kHz, dither
AT32UC3L016/32/64
Min
40
8
Figure 32-
1100
0.25
0.06
Typ
See
600
0.1
0.2
0.1
22
4
Max
150
150
100
0.5
0.5
1
1
µA/MHz
Unit
MHz
kHz
µs
%
%
793