AT32UC3L032-D3UR Atmel, AT32UC3L032-D3UR Datasheet - Page 23

• Manufacturer Part Number: AT32UC3L032-D3UR
• Description: MCU AVR32 32KB FLASH 48TLLGA
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L032-D3UR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TLLGA
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 7
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: AT32UC3L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 9 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

4.4
4.4.1
4.4.2
32099F–11/2010
Programming Model
Register File Configuration
Status Register Configuration
The AVR32UC register file is shown below.
Figure 4-3.
The Status Register (SR) is split into two halfwords, one upper and one lower, see
and
and L bits, while the upper halfword contains information about the mode and state the proces-
sor executes in. Refer to the AVR32 Architecture Manual for details.
Figure 4-4.
Application
Bit 31
Bit 31
SP_APP
SS
INT0PC
INT1PC
FINTPC
0
SMPC
R12
R11
R10
PC
LR
SR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
Figure
LC
Bit 0
1
0
-
Supervisor
Bit 31
0
4-5. The lower word contains the C, Z, N, V, and Q condition code flags and the R, T,
-
SP_SYS
INT0PC
INT1PC
FINTPC
SMPC
R12
R11
R10
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
The AVR32UC Register File
The Status Register High Halfword
0
-
Bit 0
DM
0
INT0
Bit 31
SP_SYS
INT0PC
INT1PC
FINTPC
SMPC
D
0
R12
R11
R10
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
Bit 0
0
-
INT1
Bit 31
M 2
0
SP_SYS
FINTPC
INT0PC
INT1PC
SMPC
R12
R11
R10
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
M 1
0
Bit 0
M 0
1
INT2
Bit 31
SP_SYS
FINTPC
INT0PC
INT1PC
SMPC
EM
R12
R11
R10
1
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
SS_STATUS
Bit 0
SS_SP_SYS
SS_SP_APP
SS_ADRR
SS_ADRF
SS_ADR0
SS_ADR1
I3M
SS_RAR
SS_RSR
0
INT3
Bit 31
I2M
FE
0
SP_SYS
INT0PC
INT1PC
FINTPC
SMPC
R12
R11
R10
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
AT32UC3L016/32/64
I1M
0
Bit 0
I0M
0
Exception
Bit 31
SP_SYS
INT0PC
INT1PC
FINTPC
SMPC
Bit 16
R12
R11
R10
G M
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
1
Bit 0
Bit nam e
Initial value
G lobal Interrupt M ask
Interrupt Level 0 M ask
Interrupt Level 1 M ask
Interrupt Level 2 M ask
Interrupt Level 3 M ask
Exception M ask
M ode Bit 0
M ode Bit 1
M ode Bit 2
Reserved
Debug State
Debug State M ask
Reserved
Secure State
NMI
Bit 31
SP_SYS
INT0PC
INT1PC
FINTPC
SMPC
R12
R11
R10
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
Bit 0
Figure 4-4
Secure
Bit 31
SP_SEC
INT0PC
INT1PC
FINTPC
SMPC
R12
R11
R10
PC
SR
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
Bit 0
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