AT32UC3L032-D3UR Atmel, AT32UC3L032-D3UR Datasheet - Page 492

• Manufacturer Part Number: AT32UC3L032-D3UR
• Description: MCU AVR32 32KB FLASH 48TLLGA
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L032-D3UR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TLLGA
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 7
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: AT32UC3L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 9 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

21.9.8
Name:
Access Type:
Offset:
Reset Value:
• MENB: Master Interface Enable
• STOP: Stop Request Accepted
• PECERR: PEC Error
• TOUT: Timeout
• SMBALERT: SMBus Alert
• ARBLST: Arbitration Lost
• DNAK: NAK in Data Phase Received
• ANAK: NAK in Address Phase Received
• BUSFREE: Two-wire Bus is Free
32099F–11/2010
31
23
15
7
-
-
-
-
0: Master interface is disabled.
1: Master interface is enabled.
This bit is set when STOP request caused by setting CR STOP has been accepted, and transfer has stopped.
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
This bit is set when a SMBus PEC error occurred.
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
This bit is set when a SMBus timeout occurred.
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
This bit is set when an SMBus Alert was received.
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
This bit is set when the actual state of the SDA line did not correspond to the data driven onto it, indicating a higher-priority
transmission in progress by a different master.
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
This bit is set when no ACK was received form slave during data transmission.
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
This bit is set when no ACK was received from slave during address phase
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
This bit is set when activity has completed on the two-wire bus.
Otherwise, this bit is cleared.
Status Register (SR)
STOP
30
22
14
6
-
-
-
SR
Read-only
0x1C
0x00000002
BUSFREE
PECERR
29
21
13
5
-
-
TOUT
IDLE
28
20
12
4
-
-
SMBALERT
CCOMP
27
19
11
3
-
-
ARBLST
CRDY
26
18
10
2
-
-
AT32UC3L016/32/64
TXRDY
DNAK
25
17
9
1
-
-
RXRDY
MENB
ANAK
24
16
8
0
-
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