AT32UC3L032-D3UR Atmel, AT32UC3L032-D3UR Datasheet - Page 522

• Manufacturer Part Number: AT32UC3L032-D3UR
• Description: MCU AVR32 32KB FLASH 48TLLGA
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L032-D3UR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TLLGA
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 7
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: AT32UC3L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 9 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

22.9.7
Name:
Access Type:
Offset:
Reset Value:
• BTF: Byte Transfer Finished
• REP: Repeated Start Received
• STO: Stop Received
• SMBDAM: SMBus Default Address Match
• SMBHHM: SMBus Host Header Address Match
• SMBALERTM: SMBus Alert Response Address Match
• GCM: General Call Match
• SAM: Slave Address Match
• BUSERR: Bus Error
32099F–11/2010
ORUN
BTF
31
23
15
7
-
This bit is set when byte transfer has completed.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when REPEATED START condition received.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when STOP condition received.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when received address matched SMBus Default Address.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when received address matched SMBus Host Header Address.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when received address matched SMBus Alert Response Address.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when received address matched General Call Address.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when received address matched Slave Address.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when a misplaced start or stop condition has occurred.
This bit is cleared when the corresponding bit in SCR is written to one.
Status Register
BUSERR
URUN
REP
30
22
14
6
SR
Read-only
0x18
0x000000002
SMBPECERR
STO
TRA
29
21
13
5
SMBTOUT
SMBDAM
28
20
12
4
-
-
SMBHHM
TCOMP
27
19
11
3
-
SMBALERTM
SEN
26
18
10
2
-
AT32UC3L016/32/64
TXRDY
GCM
25
17
9
1
-
RXRDY
SAM
NAK
24
16
8
0
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