AT32UC3L032-D3UR Atmel, AT32UC3L032-D3UR Datasheet - Page 114

• Manufacturer Part Number: AT32UC3L032-D3UR
• Description: MCU AVR32 32KB FLASH 48TLLGA
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L032-D3UR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TLLGA
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 7
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: AT32UC3L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 9 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

9.6.5
Name:
Access Type:
Offset:
Reset Value:
• IDLE
• SEN: SAU Setup Mode Enable
• EN: SAU Enabled
• RTRADR: RTR Address Error
• MBERROR: Master Interface Bus Error
• URES: Unlock Register Error Status
• URKEY: Unlock Register Key Error
• URREAD: Unlock Register Read
32099F–11/2010
RTRADR
31
23
15
7
-
-
-
This bit is cleared when the operation is completed and no SAU bus operations are pending.
This bit is set when a read or write operation to the SAU channel is started.
This bit is cleared when the SAU exits setup mode.
This bit is set when the SAU enters setup mode.
This bit is cleared when the SAU is disabled.
This bit is set when the SAU is enabled.
This bit is cleared when the corresponding bit in ICR is written to one.
This bit is set if, in the configuration phase, an RTR was written with an illegal address, i.e. the upper 16 bits in the address were
different from 0xFFFC, 0xFFFD, 0xFFFE or 0xFFFF.
This bit is cleared when the corresponding bit in ICR is written to one.
This bit is set if a channel access generated a transfer on the master interface that received a bus error response from the
addressed slave.
This bit is cleared when the corresponding bit in ICR is written to one.
This bit is set if an attempt was made to unlock a channel by writing to the Unlock Register while one or more error bits were set
in SR. The unlock operation was aborted.
This bit is cleared when the corresponding bit in ICR is written to one.
This bit is set if the Unlock Register was attempted written with an invalid key.
This bit is cleared when the corresponding bit in ICR is written to one.
This bit is set if the Unlock Register was read.
Status Register
MBERROR
30
22
14
6
-
-
-
SR
Read-only
0x10
0x00000000
URES
29
21
13
5
-
-
-
URKEY
28
20
12
4
-
-
-
URREAD
27
19
11
3
-
-
-
IDLE
CAU
26
18
10
2
-
-
AT32UC3L016/32/64
SEN
CAS
25
17
9
1
-
-
EXP
EN
24
16
8
0
-
-
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