AT32UC3L032-D3UR Atmel, AT32UC3L032-D3UR Datasheet - Page 829

• Manufacturer Part Number: AT32UC3L032-D3UR
• Description: MCU AVR32 32KB FLASH 48TLLGA
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L032-D3UR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TLLGA
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 7
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: AT32UC3L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 9 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

35.2.12
35.2.13
32099F–11/2010
aWire
ADCIFB
2. CAT QMatrix sense capacitors discharged prematurely
1. aWire CPU clock speed robustness
2. The aWire debug interface is reset after leaving Shutdown mode
1. Using STARTUPTIME value larger than 0x1F will freeze ADC
2. ADCIFB DMA transfers does not work with divided PBA clock
If the CAT detects a condition that should asynchronously wake the chip in Static mode, the
asynchronous wake will not occur until the next AST event. For example, if the AST is gen-
erating peripheral events to the CAT every 50 milliseconds, and the CAT detects a touch at
t=9200 milliseconds, the asynchronous wake will occur at t=9250 milliseconds.
Fix/Workaround
None.
At the end of a QMatrix burst charging sequence that uses different burst count values for
different Y lines, the Y lines may be incorrectly grounded for up to n-1 periods of the periph-
eral bus clock, where n is the ratio of the PB clock frequency to the GCLK_CAT frequency.
This results in premature loss of charge from the sense capacitors and thus increased vari-
ability of the acquired count values. For example, if the PB clock frequency is 24MHz and
GCLK_CAT frequency is 6 MHz, n=4 and the Y lines may be incorrectly grounded for 0, 1, 2,
or 3 periods of the PB clock, depending on the relative phase of the PB and GCLK_CAT
clocks.
Fix/Workaround
Enable the 1kOhm drive resistors on all implemented QMatrix Y lines (CSA 1, 3, 5, 7, 9, 11,
and/or 15) by writing ones to the corresponding odd bits of the CSARES register. For exam-
ple, if all 8 Y lines are implemented, write 0x0000AAAA to the CSARES register. When the Y
lines are incorrectly grounded by the CAT module for up to n-1 PB clocks at the end of burst
charging sequence, this will greatly reduce the amount of charge that is prematurely lost
from the sense capacitors, because the discharge time constant will now be approximately
1000Ohm times the value of the of the sense capacitor instead of a very small resistance
times the value of the sense capacitor.
The aWire memory speed request command counter wraps at clock speeds below approxi-
mately 5kHz.
Fix/Workaround
None.
If the aWire debug mode is used as debug interface and the program enters Shutdown
mode, the aWire interface will be reset when the device receives a wakeup either from the
WAKE_N pin or the AST.
Fix/Workaround
None.
Writing a value larger than 0x1F to the Startup Time field in the ADC Configuration Register
(ACR.STARTUP) will freeze the ADC, and the Busy Status bit in the Status Register
(SR.BUSY) will never be cleared.
Fix/Workaround
Do not write values larger than 0x1F to ACR.STARTUP.
DMA requests from the ADCIFB will not be performed when the PBA clock is slower than
the HSB clock.
Fix/Workaround
AT32UC3L016/32/64
829