AT32UC3L032-D3UR Atmel, AT32UC3L032-D3UR Datasheet - Page 152

• Manufacturer Part Number: AT32UC3L032-D3UR
• Description: MCU AVR32 32KB FLASH 48TLLGA
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L032-D3UR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TLLGA
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 7
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: AT32UC3L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 9 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

12.6
12.6.1
Figure 12-2. Synchronous Clock Generation
12.6.1.1
12.6.1.2
32099F–11/2010
Main Clock
Sources
Functional Description
Synchronous Clocks
Selecting the main clock source
Selecting synchronous clock division ratio
MCSEL
The System RC Oscillator (RCSYS) or a set of other clock sources provide the source for the
main clock, which is the common root for the synchronous clocks for the CPU/HSB and PBx
modules. For details about the other main clock sources, please refer to the register description
of the Main Clock Control Register (MCCTRL). The main clock is divided by an 8-bit prescaler,
and each of these synchronous clocks can run from any tapping of this prescaler, or the undi-
vided main clock, as long as f
fly, responding to varying load in the application. The clock domains can be shut down in sleep
mode, as described in
nous clock domain can be individually masked, to avoid power consumption in inactive modules.
The common main clock can be connected to RCSYS or a set of other clock sources. For details
about the other main clock sources, please refer to the register description of the Main Clock
Control Register (MCCTRL). By default, the main clock will be connected to RCSYS. The user
can connect the main clock to an other source by writing the MCSEL field in the MCCTRL regis-
ter. This must only be done after that unit has been enabled and is ready, otherwise a deadlock
will occur. Care should also be taken that the new frequency of the synchronous clocks does not
exceed the maximum frequency for each clock domain.
The main clock feeds an 8-bit prescaler, which can be used to generate the synchronous clocks.
By default, the synchronous clocks run on the undivided main clock. The user can select a pres-
caler division for the CPU clock by writing CPUDIV in CPUSEL register to one and CPUSEL in
CPUSEL register to the value, resulting in a CPU clock frequency:
Prescaler
f
CPU
= f
Instruction
main
Sleep
/ 2
(CPUSEL+1)
CPUSEL
Section
CPUDIV
CPU
12.6.3. Additionally, the clocks for each module in each synchro-
0
1
≥ f
Controller
Main Clock
PBx,
Sleep
. The synchronous clock source can be changed on-the
CPUMASK
AT32UC3L016/32/64
Mask
CPU Clocks
HSB Clocks
PBx Clocks
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