AT32UC3L032-D3UR Atmel, AT32UC3L032-D3UR Datasheet - Page 187

• Manufacturer Part Number: AT32UC3L032-D3UR
• Description: MCU AVR32 32KB FLASH 48TLLGA
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L032-D3UR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TLLGA
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 7
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: AT32UC3L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 9 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

13.5.3.1
13.5.3.2
32099F–11/2010
Enabling the DFLL
Internal synchronization
The DFLL can operate in both open loop mode and closed-loop mode. In closed-loop mode a
low frequency clock with high accuracy can be used as reference clock to get high accuracy on
the output clock (CLK_DFLL).
To prevent unexpected writes due to software bugs, write access to the configuration registers is
protected by a locking mechanism. For details please refer to the UNLOCK register description.
Figure 13-1. DFLLIF Block Diagram
The DFLL is enabled by writing a one to the Enable bit (EN) in the DFLLn Configuration Register
(DFLLnCONF). No other bits or fields in DFLLnCONF must be changed simultaneously, or
before the DFLL is enabled.
Due to multiple clock domains in the DFLLIF, values in the DFLLIF configuration registers need
to be synchronized to other clock domains. The status of this synchronization can be read from
the Power and Clocks Status Register (PCLKSR). Before writing to a DFLLIF configuration reg-
ister, the user must check that the DFLLn Synchronization Ready bit (DFLLnRDY) in PCLKSR is
set. When this bit is set, the DFLL can be configured, and CLK_DFLL is ready to be used. Any
write to a DFLLIF configuration register while DFLLnRDY is cleared will be ignored.
• 40-150MHz frequency
• Can operate standalone as a high-frequency programmable oscillator in open loop mode
• Can operate as an accurate frequency multiplier against a known frequency in closed-loop
• Optional spread-spectrum clock generation
• Very high-frequency multiplication supported - can generate all frequencies from a 32 KHz
mode
clock
8+9
32
CSIZE
FSIZE
FMUL
IMUL
DFLLLOCKLOSTC
DFLLLOCKC
FREQUENCY
DFLLLOCKLOSTF
TUNER
DFLLLOCKF
COARSE
FINE
DFLLUNDERFLOW
DFLLOVERFLOW
8
9
DAC
AT32UC3L016/32/64
CLK_DFLLIF_REF
VCO
187