AT32UC3L032-D3UR Atmel, AT32UC3L032-D3UR Datasheet - Page 159

• Manufacturer Part Number: AT32UC3L032-D3UR
• Description: MCU AVR32 32KB FLASH 48TLLGA
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L032-D3UR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TLLGA
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 7
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: AT32UC3L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 9 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

12.6.6.1
12.6.6.2
12.6.7
12.6.8
32099F–11/2010
Clock Failure Detector
Interrupts
Power-On Detector
External Reset
When a Reset occurs, some parts of the chip are not necessarily reset, depending on the reset
source. Only the Power On Reset (POR) will force a reset of the whole chip. Refer to the module
configuration chapter to know the effect of the different reset events.
The table located in the module configuration chapter lists parts of the device that are reset,
depending on the reset source.The cause of the last reset can be read from the RCAUSE regis-
ter. This register contains one bit for each reset source, and can be read during the boot
sequence of an application to determine the proper action to be taken.
The Power-On Detector monitors the VDDCORE supply pin and generates a reset when the
device is powered on. The reset is active until the supply voltage from the linear regulator is
above the power-on threshold level. The reset will be re-activated if the voltage drops below the
power-on threshold level. See Electrical Characteristics for parametric details.
The external reset detector monitors the state of the RESET_N pin. By default, a low level on
this pin will generate a reset.
This mechanism allows switching the main clock to the safe RCSYS clock, when the main clock
source is considered off. This may happen when a external crystal is selected as the clock
source of the main clock but the crystal is not mounted on the board. The mechanism is to
detect, during a RCSYS period, at least one rising edge of the main clock. If no rising edge is
seen the clock is considered failed.
Example:
* RCSYS = 115khz
=> Failure detected if the main clock is < 115 kHz
As soon as the detector is enabled, the clock failure detector will monitor the divided main clock.
Note that the detector does not monitor if the RCSYS is the source of the main clock, or if the
main clock is temporarily not available (startup-time after a wake-up, switching timing etc.), or in
sleep mode where the main clock is driven by the RCSYS (Stop and DeepStop mode). When a
clock failure is detected, the main clock automatically switches to the RCSYS clock and the CFD
interrupt is generated if enabled.
The MCCTRL register that selects the source clock of the main clock is changed by hardware to
indicate that the main clock comes from RCSYS.
The PM has a number of interrupts:
• AE: Access Error, set if a lock protected register is written without first being unlocked.
• CKRDY: Clock Ready, set when new CKSEL settings are effective.
• CFD: Clock Failure Detected, set if the system detects that the main clock is not running.
AT32UC3L016/32/64
159