AT32UC3L032-D3UR Atmel, AT32UC3L032-D3UR Datasheet - Page 833

• Manufacturer Part Number: AT32UC3L032-D3UR
• Description: MCU AVR32 32KB FLASH 48TLLGA
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L032-D3UR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TLLGA
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 7
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: AT32UC3L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 9 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

32099F–11/2010
2. Disabling POR33 may generate spurious resest
3. CONFIG register reads 0x4F
4. PB writes via debugger in sleep modes are blocked during sleepwalking
5. VERSION register reads 0x400
6. WCAUSE register should not be used
7. Static mode cannot be entered if the WDT is using OSC32K
8. It is not possible to mask the request clock requests
9. Clock failure detector (CFD) does not work
10. Instability when exiting sleep walking
Depending on operating conditions, POR33 may generate a spurious reset in one of the fol-
lowing cases:
- When POR33 is disabled from the user interface.
- When SM33 supply monitor is enabled.
- When entering Shutdown mode while debugging the chip using JTAG or aWire interface.
In the listed cases, writing a one to the bit VREGCR.POR33MASK in the System Control
Interface (SCIF) to mask the POR33 reset will be ineffective.
Fix/Workaround
- Do not disable POR33 using the user interface.
- Do not use the SM33 supply monitor.
- Do not enter Shutdown mode if a debugger is connected to the chip.
The CONFIG register reads 0x4F instead of 0x43.
Fix/Workaround
None.
During sleepwalking, PB writes performed by a debugger will be discarded by all PB mod-
ules except the module that is requesting the clock.
Fix/Workaround
None.
The VERSION register reads 0x400 instead of 0x411.
Fix/Workaround
None.
The WCAUSE register should not be used.
Fix/Workaround
None.
If the WDT is using OSC32K as clock source and the user tries to enter Static mode, the
Deepstop mode will be entered instead.
Fix/Workaround
None.
It is not possible to mask the request clock requests using PPCR.
Fix/Workaround
None.
The clock failure detector does not work.
Fix/Workaround
None.
If all the following operating conditions are true, exiting sleep walking might lead to
instability:
AT32UC3L016/32/64
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