AT32UC3L032-D3UR Atmel, AT32UC3L032-D3UR Datasheet - Page 153

• Manufacturer Part Number: AT32UC3L032-D3UR
• Description: MCU AVR32 32KB FLASH 48TLLGA
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L032-D3UR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TLLGA
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 7
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: AT32UC3L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 9 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

12.6.1.3
12.6.2
12.6.2.1
12.6.3
12.6.3.1
32099F–11/2010
Peripheral Clock Masking
Sleep Modes
Clock Ready flag
Cautionary note
Entering and exiting sleep modes
Similarly, the clock for the PBx can be divided by writing their respective registers. To ensure
correct operation, frequencies must be selected so that f
exceed the specified maximum frequency for each clock domain.
CPUSEL and PBxSEL can be written without halting or disabling peripheral modules. Writing
CPUSEL and PBxSEL allows a new clock setting to be written to all synchronous clocks at the
same time. It is possible to keep one or more clocks unchanged by writing a one to the registers.
This way, it is possible to, e.g., scale CPU and HSB speed according to the required perfor-
mance, while keeping the PBx frequency constant.
For modules connected to the HSB bus, the PB clock frequency must be set to the same fre-
quency as the CPU clock.
There is a slight delay from CPUSEL and PBxSEL is written and the new clock setting becomes
effective. During this interval, the Clock Ready (CKRDY) flag in ISR will read as zero. If CKRDY
in the IER register is written to one, the Power Manager interrupt can be triggered when the new
clock setting is effective. CKSEL must not be re-written while CKRDY is zero, or the system may
become unstable or hang.
By default, the clock for all modules are enabled, regardless of which modules are actually being
used. It is possible to disable the clock for a module in the CPU, HSB or PBx clock domain by
writing the corresponding bit in the Clock Mask register (CPU/HSB/PBx) to zero. When a module
is not clocked, it will cease operation, and its registers cannot be read or written. The module
can be re-enabled later by writing the corresponding mask bit to one.
A module may be connected to several clock domains, in which case it will have several mask
bits.
The Maskable Module Clocks table contains a list of implemented maskable clocks.
Note that clocks should only be switched off if it is certain that the module will not be used.
Switching off the clock for the flash controller will cause a problem if the CPU needs to read from
the flash. Switching off the clock to the Power Manager (PM), which contains the mask registers,
or the corresponding PBx bridge, will make it impossible to write the mask registers again. In this
case, they can only be re-enabled by a system reset.
In normal operation, all clock domains are active, allowing software execution and peripheral
operation. When the CPU is idle, it is possible to switch off the CPU clock and optionally other
clock domains to save power. This is activated by the sleep instruction, which takes the sleep
mode index number from
The sleep instruction will halt the CPU and all modules belonging to the stopped clock domains.
The modules will be halted regardless of the bit settings of the mask registers.
Clock sources can also be switched off to save power. Some of these have a relatively long
start-up time, and are only switched off when very low power consumption is required.
Table 12-2 on page 154
as argument.
CPU
AT32UC3L016/32/64
≥ f
PBx
. Also, frequencies must never
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