AT32UC3L032-D3UR Atmel, AT32UC3L032-D3UR Datasheet - Page 839

• Manufacturer Part Number: AT32UC3L032-D3UR
• Description: MCU AVR32 32KB FLASH 48TLLGA
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L032-D3UR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TLLGA
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 7
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: AT32UC3L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 9 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

32099F–11/2010
4. TWI pins are not SMBus compliant
5. PA21, PB04, and PB05 are not 5V tolerant
6. PB04 SMBALERT function should not be used
7. TWIMS0.TWCK on PB05 is non-functional
8. TWIM STOP bit in IMR always read as zero
9. TWIM.SR.IDLE goes high immediately when NAK is received
10. Disabled TWIM drives TWD and TWCK low
2. TWIM SMBAL polarity is wrong
Fix/Workaround
Do not write both CR.STREN and CR.SOAM to one if the device needs to wake from deep
sleep modes.
The TWI pins draws current when the pins are supplied with 3.3 V and the part is left
unpowered.
Fix/Workaround
None.
Pins PA21, PB04, and PB05 are only 3.3V tolerant, not 5V tolerant.
Fix/Workaround
None.
The SMBALERT function from TWIMS0 should not be selected on pin PB04.
Fix/Workaround
None.
TWIMS0.TWCK on PB05 is non-functional.
Fix/Workaround
Use TWI0.TWCK on other pins.
The STOP bit in IMR always reads as zero.
Fix/Workaround
None.
When a NAK is received and there is a non-zero number of bytes to be transmitted,
SR.IDLE goes high immediately and does not wait for the STOP condition to be sent. This
does not cause any problem just by itself, but can cause a problem if software waits for
SR.IDLE to go high and then immediately disables the TWIM by writing a one to CR.MDIS.
Disabling the TWIM causes the TWCK and TWD pins to go high immediately, so the STOP
condition will not be transmitted correctly.
Fix/Workaround
If possible, do not disable the TWIM. If it is absolutely necessary to disable the TWIM, there
must be a software delay of at least two TWCK periods between the detection of
SR.IDLE==1 and the disabling of the TWIM.
When the TWIM is disabled, it drives the TWD and TWCK signals with logic level zero. This
can lead to communication problems with other devices on the TWI bus.
Fix/Workaround
Enable the TWIM first and then enable the TWD and TWCK peripheral pins in the GPIO
controller. If it is necessary to disable the TWIM, first disable the TWD and TWCK peripheral
pins in the GPIO controller and then disable the TWIM.
The SMBAL signal in the TWIM is active high instead of active low.
Fix/Workaround
AT32UC3L016/32/64
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