AT32UC3L032-D3UR Atmel, AT32UC3L032-D3UR Datasheet - Page 105

• Manufacturer Part Number: AT32UC3L032-D3UR
• Description: MCU AVR32 32KB FLASH 48TLLGA
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L032-D3UR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TLLGA
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 7
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: AT32UC3L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 9 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

9.4
9.4.1
9.4.2
9.4.3
9.4.4
9.5
9.5.1
9.5.2
32099F–11/2010
Product Dependencies
Functional Description
Power Management
Clocks
Interrupt
Debug Operation
Enabling the SAU
Configuring the SAU Channels
In order to use this module, other parts of the system must be configured correctly, as
described below.
If the CPU enters a sleep mode that disables clocks used by the SAU, the SAU will stop func-
tioning and resume operation after the system wakes up from sleep mode.
The SAU has two bus clocks connected: One High Speed Bus clock (CLK_SAU_HSB) and
one Peripheral Bus clock (CLK_SAU_PB). These clocks are generated by the Power Man-
ager. Both clocks are enabled at reset, and can be disabled by writing to the Power Manager.
The user has to ensure that CLK_SAU_HSB is not turned off before accessing the SAU. Like-
wise, the user must ensure that no bus access is pending in the SAU before disabling
CLK_SAU_HSB. Failing to do so may deadlock the High Speed Bus.
The SAU interrupt request line is connected to the interrupt controller. Using the SAU interrupt
requires the interrupt controller to be programmed first.
When an external debugger forces the CPU into debug mode, the SAU continues normal
operation. If the SAU is configured in a way that requires it to be periodically serviced by the
CPU through interrupts or similar, improper operation or data loss may result during
debugging.
The SAU is enabled by writing a one to the Enable (EN) bit in the Control Register (CR). This
will set the SAU Enabled (EN) bit in the Status Register (SR).
The SAU has a set of channels, mapped in the HSB memory space. These channels can be
configured by a Remap Target Register (RTR), located at the same memory address. When
the SAU is in normal mode, the SAU channel is addressed, and when the SAU is in setup
mode, the RTR can be addressed.
Before the SAU can be used, the channels must be configured and enabled. To configure a
channel, the corresponding RTR must be programmed with the Remap Target Address. To do
this, make sure the SAU is in setup mode by writing a one to the Setup Mode Enable (SEN) bit
in CR. This makes sure that a write to the RTR address accesses the RTR, not the SAU chan-
nel. Thereafter, the RTR is written with the address to remap to, typically the address of a
specific PB register. When all channels have been configured, return to normal mode by writ-
ing a one to the Setup Mode Disable (SDIS) in CR. The channels can now be enabled by
writing ones to the corresponding bits in the Channel Enable Registers (CERH/L).
The SAU is only able to remap addresses above 0xFFFC0000.
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