AT32UC3L032-D3UR Atmel, AT32UC3L032-D3UR Datasheet - Page 61

• Manufacturer Part Number: AT32UC3L032-D3UR
• Description: MCU AVR32 32KB FLASH 48TLLGA
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L032-D3UR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TLLGA
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 7
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: AT32UC3L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 9 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

7.7.17
Name:
Access Type:
Offset:
Reset Value:
• MON1CH: Performance Monitor Channel 1
• MON0CH: Performance Monitor Channel 0
• CH1RES: Performance Channel 1 Counter Reset
• CH0RES: Performance Channel 0 Counter Reset
• CH1OF: Performance Channel 1 Overflow Freeze
• CH1OF: Performance Channel 0 Overflow Freeze
• CH1EN: Performance Channel 1 Enable
• CH0EN: Performance Channel 0 Enable
32099F–11/2010
31
23
15
7
-
-
-
-
The PDCA channel number to monitor with counter n
Due to performance monitor hardware resource sharing, the two performance monitor channels should NOT be programmed to
monitor the same PDCA channel. This may result in UNDEFINED monitor behavior.
Writing a zero to this bit has no effect.
Writing a one to this bit will reset the counter in performance channel 1.
This bit always reads as zero.
Writing a zero to this bit has no effect.
Writing a one to this bit will reset the counter in performance channel 0.
This bit always reads as zero.
0: The performance channel registers are reset if DATA or STALL overflows.
1: All performance channel registers are frozen just before DATA or STALL overflows.
0: The performance channel registers are reset if DATA or STALL overflows.
1: All performance channel registers are frozen just before DATA or STALL overflows.
0: Performance channel 1 is disabled.
1: Performance channel 1 is enabled.
0: Performance channel 0 is disabled.
1: Performance channel 0 is enabled.
Performance Control Register
30
22
14
6
-
-
-
-
PCONTROL
Read/Write
0x800
0x00000000
CH1OF
29
21
13
5
-
CH0OF
28
20
12
4
-
27
19
11
3
-
-
MON1CH
MON0CH
26
18
10
2
-
-
AT32UC3L016/32/64
CH1RES
CH1EN
25
17
9
1
CH0RES
CH0EN
24
16
8
0
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