AT32UC3L032-D3UR Atmel, AT32UC3L032-D3UR Datasheet - Page 197

• Manufacturer Part Number: AT32UC3L032-D3UR
• Description: MCU AVR32 32KB FLASH 48TLLGA
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L032-D3UR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TLLGA
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 7
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: AT32UC3L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 9 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

13.5.11
13.5.12
13.5.13
32099F–11/2010
Backup Registers (BR)
32kHz RC Oscillator (RC32K)
Generic Clocks
Rev: AVR32.1
Four 32-bit backup registers are available to store values when the chip is in Shutdown mode.
These registers will keep their content even when the VDDCORE and VDDIO supplies are
removed. The backup registers can be accessed by reading and writing the BR0, BR1, BR2,
and BR3 registers.
After writing to one of the backup registers the user must wait until the Backup Register Interface
Ready (BRIFARDY) bit in PCLKSR is set before writing to another backup register. Writes to the
backup register while BRIFARDY is zero will be discarded. An interrupt can be generated on a
zero-to-one transition on BRIFARDY.
After powering up the device the Backup Register Interface Valid (BRIFAVALID) bit in PCLKSR
is cleared, indicating that the contents of the backup registers has not been written and contains
the reset value. After writing one of the backup registers the BRIFAVALID bit is set. During
writes to the backup registers (when BRIFARDY is zero) BRIFAVALID will be zero. If a reset
occurs when BRIFRDY is zero, BRIFAVALID will be cleared after the reset, indicating that the
contents of the backup registers are not valid. If BRIFARDY was one when the reset occurred,
BRIFAVALID will be one and the contents are the same as before the reset.
The user must ensure that BRIFAVALID and BRIFARDY are both set before reading the backup
register values.
Rev: 1.0.0.0
The RC32K can be used as source for the generic clocks, as described in The Generic Clocks
section.
The 32 kHz RC oscillator (RC32K) is forced on after reset, and output on PA20. The clock is
available on the pad until the PPCR.RC32OUT bit in the Power Manager has been cleared or a
different peripheral function has been chosen on port PA20 (port PA20 will start with peripheral
function “F” by default). Note that the forcing will only enable the clock output. To be able to use
the RC32K normally the oscillator must be enabled as described below.
The oscillator is enabled by writing a one to the Enable bit (EN) bit in the 32 kHz RC Oscillator
Configuration Register (RC32KCR) and disabled by writing a zero to RC32KCR.EN. The oscilla-
tor is also automatically enabled when the sampling mode is requested for the SM33. In this
case, writing a zero to RC32KCR.EN will not disable the RC32K until the sampling mode is no
longer requested.
Rev: 1.0.0.0
Timers, communication modules, and other modules connected to external circuitry may require
specific clock frequencies to operate correctly. The SCIF defines a number of generic clocks that
can provide a wide range of accurate clock frequencies.
Each generic clock runs from either clock source listed in the “Generic Clock Sources” table in
the SCIF Module Configuration section. The selected source can optionally be divided by any
even integer up to 512. Each clock can be independently enabled and disabled, and is also
automatically disabled along with peripheral clocks by the Sleep Controller in the Power
Manager.
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