AT32UC3L032-D3UR Atmel, AT32UC3L032-D3UR Datasheet - Page 510

• Manufacturer Part Number: AT32UC3L032-D3UR
• Description: MCU AVR32 32KB FLASH 48TLLGA
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L032-D3UR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TLLGA
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 7
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: AT32UC3L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 9 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

22.8.5
22.8.5.1
22.8.5.2
22.8.6
22.8.6.1
32099F–11/2010
Using the Peripheral DMA Controller
SMBus Mode
Data Transmit with the Peripheral DMA Controller
Packet Error Checking
Data Receive with the Peripheral DMA Controller
The use of the Peripheral DMA Controller significantly reduces the CPU load. The program-
mer can set up ring buffers for the DMA controller, containing data to transmit or free buffer
space to place received data. By initializing NBYTES to 0 before a transfer, and setting
CR.CUP, NBYTES is incremented by 1 each time a data has been transmitted or received.
This allows the programmer to detect how much data was actually transferred by the DMA
system.
To assure correct behavior, respect the following programming sequences:
SMBus mode is enabled when CR.SMEN is written to one. SMBus mode operation is similar
to I²C operation with the following exceptions:
Each SMBus transfer can optionally end with a CRC byte, called the PEC byte. Writing a one
to CR.PECEN enables automatic PEC handling in the current transfer. The PEC generator is
always updated on every bit transmitted or received, so that PEC handling on following linked
transfers will be correct.
In slave receiver mode, the master calculates a PEC value and transmits it to the slave after
all data bytes have been transmitted. Upon reception of this PEC byte, the slave will compare
it to the PEC value it has computed itself. If the values match, the data was received correctly,
and the slave will return an ACK to the master. If the PEC values differ, data was corrupted,
1. Initialize the transmit Peripheral DMA Controller (memory pointers, size, etc.).
2. Configure the TWIS (ADR, NBYTES, etc.).
3. Start the transfer by setting the Peripheral DMA Controller TXTEN bit.
4. Wait for the Peripheral DMA Controller end TX flag.
5. Disable the Peripheral DMA Controller by setting the Peripheral DMA Controller
1. Initialize the receive Peripheral DMA Controller (memory pointers, size - 1, etc.).
2. Configure the TWIS (ADR, NBYTES, etc.).
3. Start the transfer by setting the Peripheral DMA Controller RXTEN bit.
4. Wait for the Peripheral DMA Controller end RX flag.
5. Disable the Peripheral DMA Controller by setting the Peripheral DMA Controller
• Only 7-bit addressing can be used.
• The SMBus standard describes a set of timeout values to ensure progress and throughput
• Transmissions can optionally include a CRC byte, called Packet Error Check (PEC).
• A dedicated bus line, SMBALERT, allows a slave to get a master’s attention.
• A set of addresses have been reserved for protocol handling, such as Alert Response
on the bus. These timeout values must be programmed into TR.
Address (ARA) and Host Header (HH) Address. Address matching on these addresses can
be enabled by configuring CR appropriately.
TXDIS bit.
RXDIS bit.
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