AT32UC3L032-D3UR Atmel, AT32UC3L032-D3UR Datasheet - Page 192

• Manufacturer Part Number: AT32UC3L032-D3UR
• Description: MCU AVR32 32KB FLASH 48TLLGA
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L032-D3UR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TLLGA
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 7
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: AT32UC3L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 9 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

13.5.3.8
13.5.3.9
13.5.4
32099F–11/2010
Brown-Out Detection (BOD)
Accuracy
Interrupts
There are mainly three factors that decide the accuracy of the f
obtain maximum accuracy when fine lock is acheived.
A interrupt can be generated on a zero-to-one transaction on DFLLnLOCKC, DFLLnLOCKF,
DFLLnLOCKA, DFLLnLOCKLOSTC, DFLLnLOCKLOSTF, DFLLnLOCKLOSTA, DFLLnRDY or
DFLLnRCS.
Rev: 1.0.1.0
The Brown-Out Detector monitors the VDDCORE supply pin and compares the supply voltage
to the brown-out detection level.
The BOD is disabled by default, and is enabled by writing to the BOD Control field (CTRL) in the
BOD Control Register (BOD). This field can also be updated by flash fuses.
The brown-out detection level is selected by writing to the BOD Level field (LEVEL) in BOD.
Please refer to Electrical Characteristics for parametric details.
If the BOD Control field (CTRL) in BOD is written to two and the supply voltage goes below the
detection level, the Brown-Out Detection bit (BODDET) in PCLKSR is set. This bit is cleared
when the supply voltage goes above the detection level. An interrupt can be generated on a zero
to one transition on PCLKSR.BODDET. If the BOD.CTRL field is written to one, a BOD reset will
be generated when the supply voltage goes below the detection level, resetting the device. Writ-
ing a one to the BOD Hysteresis bit (HYST) in BOD will add a hysteresis on the BOD detection
level.
Note that the BOD should be disabled before changing BOD.LEVEL, to avoid spurious reset or
interrupt. After enabling the BOD, the BOD output will be masked during one half of a RCSYS
clock cycle and two main clocks cycles to avoid false results.
When JTAG or aWire is enabled, the BOD reset and interrupt are masked.
The CTRL, HYST and LEVEL fields in the BOD Control Register are loaded from Flash Fuse
after a reset. It is still possible to override these values after reset by writing to the BOD Control
Register. Please refer to the Fuse setting chapter for more details about BOD fuses and how to
program the fuses.
If the Flash Calibration Done (FCD) bit in the BOD Control Register is zero at BOD reset then
the flash calibration will be redone and the BOD.FCD bit will be set before program execution
starts in the CPU. If the BOD.FCD is one then the BOD configuration will not be changed during
a BOD reset. To prevent unexpected writes to BOD due to software bugs, write access to this
register is protected by a locking mechanism. For details please refer to the UNLOCK register
description.
• FINE resolution: The frequency step between two FINE values. This is relatively smaller for
• Resolution of the measurement: If the resolution of the measured f
• The accuracy of the reference clock.
high output frequencies.
between CLK_DFLL frequency and CLK_DFLLIF_REF is small, then the DFLLIF might lock
at a frequency that is lower than the targeted frequency. It is recommended to use a
reference clock frequency of 32 KHz or lower to avoid this issue for low target frequencies.
AT32UC3L016/32/64
DFLL
DFLL
. These can be tuned to
is low, i.e. the ratio
192