AT32UC3L032-D3UR Atmel, AT32UC3L032-D3UR Datasheet - Page 481

• Manufacturer Part Number: AT32UC3L032-D3UR
• Description: MCU AVR32 32KB FLASH 48TLLGA
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L032-D3UR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TLLGA
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 7
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: AT32UC3L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 9 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

21.8.9.2
21.8.9.3
21.8.10
32099F–11/2010
Identifying Bus Events
Timeouts
SMBus ALERT Signal
In combined transfers, the PECEN bit should only be set in the last of the combined transfers.
Consider the following transfer:
S, ADR+W, COMMAND_BYTE, ACK, SR, ADR+R, DATA_BYTE, ACK, PEC_BYTE, NACK,
P
This transfer is generated by writing two commands to the command registers. The first com-
mand is a write with NBYTES=1 and PECEN=0, and the second is a read with NBYTES=2
and PECEN=1.
Writing a one to the STOP bit in CR will place a STOP condition on the bus after the current
byte. No PEC byte will be sent in this case.
The TLOWS and TLOWM fields in SMBTR configure the SMBus timeout values. If a timeout
occurs, the master will transmit a STOP condition and leave the bus. The SR.TOUT bit is also
set.
A slave can get the master’s attention by pulling the TWALM line low. SR.SMBAL will then be
set. This can be set up to trigger an interrupt, and software can then take the appropriate
action, as defined in the SMBus standard.
This chapter lists the different bus events, and how these affects bits in the TWIM registers.
This is intended to help writing drivers for the TWIM.
Table 21-5.
Event
Master transmitter has sent
a data byte
Master receiver has
received a data byte
Start+Sadr sent, no ack
received from slave
Data byte sent to slave, no
ack received from slave
Arbitration lost
SMBus Alert received
Bus Events
Effect
SR.THR is cleared.
SR.RHR is set.
SR.ANAK is set.
SR.CCOMP not set.
CMDR.VALID remains set.
STOP automatically transmitted on bus.
SR.DNAK is set.
SR.CCOMP not set.
CMDR.VALID remains set.
STOP automatically transmitted on bus.
SR.ARBLST is set.
SR.CCOMP not set.
CMDR.VALID remains set.
TWCK and TWD immediately released to a pulled-up state.
SR.SMBAL is set.
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