AT32UC3L032-D3UR Atmel, AT32UC3L032-D3UR Datasheet - Page 384

• Manufacturer Part Number: AT32UC3L032-D3UR
• Description: MCU AVR32 32KB FLASH 48TLLGA
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L032-D3UR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TLLGA
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 7
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: AT32UC3L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 9 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Figure 19-23. Slave Node Synchronization
32099F–11/2010
Fractional Part (FP)
Clcok Divider (CD)
Synchro Counter
Baud Rate
LINIDRX
BRGR
BRGR
Clock
RXD
When the start bit of the Synch Field is detected the counter is reset. Then during the next 8
Tbits of the Synch Field, the counter is incremented. At the end of these 8 Tbits, the counter is
stopped. At this moment, the 16 most significant bits of the counter (value divided by 8) gives the
new clock divider (CD) and the 3 least significant bits of this value (the remainder) gives the new
fractional part (FP).
When the Synch Field has been received, the clock divider (CD) and the fractional part (FP) are
updated in the Baud Rate Generator register (BRGR).
The accuracy of the synchronization depends on several parameters:
The following formula is used to compute the deviation of the slave bit rate relative to the master
bit rate after synchronization (F
F
LIN Standard imposes that it must not exceed ±15%. The LIN Standard imposes also that for
communication between two nodes, their bit rate must not differ by more than ±2%. This means
that the Baudrate_deviation must not exceed ±1%.
It follows from that, a minimum value for the nominal clock frequency:
TOL_UNSYNCH
• The nominal clock frequency (F
• The Baudrate
• The oversampling (Over=0 => 16X or Over=0 => 8X)
13 dominant bits (at 0)
Break Field
is the deviation of the real slave node clock from the nominal clock frequency. The
Baudrate_deviation
Baudrate_deviation
Initial CD
Initial FP
1 recessive bit
Delimiter
Break
(at 1)
Reset
SLAVE
Start
Bit
Nom
=
=
is the real slave node clock frequency).
1
⎛
⎝
⎛
⎜
⎜
⎜
⎝
) (the theoretical slave node clock frequency)
100
100
–
0
0,5
Synch Byte = 0x55
1
×
×
≤
α [
-------------------------------------------------------------------------------------------- -
α [
-------------------------------------------------------------------------------------------- -
0
α +0,5
≤
×
×
1
8
8
8
×
0
×
×
⎛
⎝
(
(
F
-------------------------------------- -
1
2 Over
2 Over
TOL_UNSYNCH
–
–
0
8
-1
AT32UC3L016/32/64
000_0011_0001_0110_1101
Stop
×
100
Bit
<
0000_0110_0010_1101
101
F
β
Start
SLAVE
Bit
)
)
<
+ ]
+ ]
ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7
+1
β
β
⎞ xF
⎠
×
×
Baudrate
Baudrate
Nom
⎞ %
⎠
⎞
⎟
⎟
⎟
⎠
%
Stop
Bit
384