AT32UC3L032-D3UR Atmel, AT32UC3L032-D3UR Datasheet - Page 837

• Manufacturer Part Number: AT32UC3L032-D3UR
• Description: MCU AVR32 32KB FLASH 48TLLGA
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L032-D3UR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TLLGA
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 7
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: AT32UC3L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 9 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

35.4.10
35.4.11
35.4.12
32099F–11/2010
FREQM
GPIO
USART
3. Clearing the Watchdog Timer (WDT) counter in second half of timeout period will
1.
2.
1. GPIO interrupt can not be cleared when interrupts are disabled
2. VERSION register reads 0x210
1. The RTS output does not function correctly in hardware handshaking mode
Fix/Workaround
None.
issue a Watchdog reset
If the WDT counter is cleared in the second half of the timeout period, the WDT will immedi-
ately issue a Watchdog reset.
Fix/Workaround
Use twice as long timeout period as needed and clear the WDT counter within the first half
of the timeout period. If the WDT counter is cleared after the first half of the timeout period,
you will get a Watchdog reset immediately. If the WDT counter s not cleared at all, the time
before the reset will be twice as long as needed.
CLKSEL = 14 selects the RC120M AW clock, CLKSEL = 15 selects the RC120M clock, and
CLKSEL = 16 selects the RC32K clock as source for the measured clock (CLK_MSR).
Fix/Workaround
None.
The frequency for GCLK5 can not be measured by the FREQM.
Fix/Workaround
None.
The GPIO interrupt can not be cleared unless the interrupt is enabled for the pin.
Fix/Workaround
Enable interrupt for the corresponding pin, then clear the interrupt.
The VERSION register reads 0x210 instead of 0x211.
Fix/Workaround
None.
The RTS signal is not generated properly when the USART receives data in hardware hand-
shaking mode. When the Peripheral DMA receive buffer becomes full, the RTS output
should go high, but it will stay low.
Fix/Workaround
Do not use the hardware handshaking mode of the USART. If it is necessary to drive the
RTS output high when the Peripheral DMA receive buffer becomes full, use the normal
mode of the USART. Configure the Peripheral DMA Controller to signal an interrupt when
the receive buffer is full. In the interrupt handler code, write a one to the RTSDIS bit in the
USART Control Register (CR). This will drive the RTS output high. After the next DMA trans-
fer is started and a receive buffer is available, write a one to the RTSEN bit in the USART
CR so that RTS will be driven low.
Measured clock (CLK_MSR) sources 15-17 are shifted
GCLK5 can not be used as source for the CLK_MSR
AT32UC3L016/32/64
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