AT32UC3L032-D3UR Atmel, AT32UC3L032-D3UR Datasheet - Page 32

• Manufacturer Part Number: AT32UC3L032-D3UR
• Description: MCU AVR32 32KB FLASH 48TLLGA
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L032-D3UR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TLLGA
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 7
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: AT32UC3L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 9 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

5. Memories
5.1
5.2
Table 5-2.
32099F–11/2010
Embedded Memories
Physical Memory Map
AT32UC3L064
AT32UC3L032
AT32UC3L016
Part Number
Flash Memory Parameters
•
•
The system bus is implemented as a bus matrix. All system bus addresses are fixed, and they
are never remapped in any way, not even in boot. Note that AVR32 UC CPU uses unsegmented
translation, as described in the AVR32 Architecture Manual. The 32-bit physical address space
is mapped as follows:
Table 5-1.
Device
Embedded SRAM
Embedded Flash
HSB-PB Bridge B
HSB-PB Bridge A
Internal High-Speed Flash
Internal High-Speed SRAM, Single-cycle access at full speed
– 64Kbytes (AT32UC3L064)
– 32Kbytes (AT32UC3L032)
– 16Kbytes (AT32UC3L016)
– 16Kbytes (AT32UC3L064, AT32UC3L032)
– 8Kbytes (AT32UC3L016)
• 0 Wait State Access at up to 25MHz in Worst Case Conditions
• 1 Wait State Access at up to 50MHz in Worst Case Conditions
• Pipelined Flash Architecture, allowing burst reads from sequential Flash locations, hiding
• Pipelined Flash Architecture typically reduces the cycle penalty of 1 wait state operation
• 100 000 Write Cycles, 15-year Data Retention Capability
• Sector Lock Capabilities, Bootloader Protection, Security Bit
• 32 Fuses, Erased During Chip Erase
• User Page For Data To Be Preserved During Chip Erase
penalty of 1 wait state access
to only 8% compared to 0 wait state operation
Flash Size (FLASH_PW)
AT32UC3L Physical Memory Map
64Kbytes
32Kbytes
16Kbytes
Start Address
0x00000000
0x80000000
0xFFFE0000
0xFFFF0000
Size
AT32UC3L064
64Kbytes
64Kbytes
64Kbytes
16Kbytes
Number of pages
(FLASH_P)
256
128
64
AT32UC3L032
16Kbytes
32Kbytes
64Kbytes
64Kbytes
AT32UC3L016/32/64
AT32UC3L016
8Kbytes
16Kbytes
64Kbytes
64Kbytes
(FLASH_W)
Page size
256 bytes
256 bytes
256 bytes
32