AT32UC3L032-D3UR Atmel, AT32UC3L032-D3UR Datasheet - Page 666

• Manufacturer Part Number: AT32UC3L032-D3UR
• Description: MCU AVR32 32KB FLASH 48TLLGA
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L032-D3UR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TLLGA
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 7
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: AT32UC3L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 9 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

28.6.6
32099F–11/2010
Spread Spectrum Sensor Drive
Figure 28-4. CAT Acquisition and Processing Sequence
To reduce electromagnetic compatibility issues, the capacitive sensors can be driven with a
spread spectrum signal. To enable spread spectrum drive for a specific acquisition type, the
user must write a one to the SPREAD bit in the appropriate Configuration Register 1 (MGCFG1,
ATCFG1, TGACFG1, or TGBCFG1).
During spread spectrum operation, the length of each pulse within a burst is varied in a deter-
ministic pattern, so that the exact same burst pattern is used for a specific burst length. The
maximum spread is determined by the MAXDEV field in the Spread Spectrum Configuration
Register (SSCFG) register. The prescaler divisor is varied in a sawtooth pattern from
(2(DIV+1))-MAXDEV to (2(DIV+1))+MAXDEV and then back to (2(DIV+1))-MAXDEV. For exam-
ple, if DIV is 2 and MAXDEV is 3, the prescaler divisor will have the following sequence: 6, 7, 8,
No
touch detection
Autonomous touch
enabled (ATEN)?
autonomous
autonomous
touch count
Yes
algorithm
Acquire
Update
No
Idle
AISR written flag set?
Yes
AT32UC3L016/32/64
to be transferred
acquired counts
Acquire counts
Clear AISR
written flag
Wait for all
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