AT32UC3L032-D3UR Atmel, AT32UC3L032-D3UR Datasheet - Page 254

• Manufacturer Part Number: AT32UC3L032-D3UR
• Description: MCU AVR32 32KB FLASH 48TLLGA
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L032-D3UR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TLLGA
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 7
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: AT32UC3L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 9 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

14.6
Table 14-1.
Note:
32099F–11/2010
Offset
0xFC
0x0C
0x1C
0x4C
0xF0
0x00
0x04
0x08
0x10
0x14
0x18
0x20
0x24
0x30
0x34
0x40
0x44
0x48
0x50
0x54
User Interface
1. The reset values are device specific. Please refer to the Modue Configuration section at the end of this chapter.
2. The number of Alarm and Periodic Interval registers are device specific. Please refer to the Module Configuration section at
the end of this chapter.
AST Register Memory Map
Periodic Interval Register 0
Periodic Interval Register 1
Interrupt Disable Register
Interrupt Enable Register
Interrupt Mask Register
Clock Control Register
Wake Enable Register
Status Clear Register
Digital Tuner Register
Parameter Register
Alarm Register 0
Alarm Register 1
Version Register
Control Register
Status Register
Calendar Value
Counter Value
Event Disable
Event Enable
Event Mask
Register
(2)
(2)
(2)
(2)
Register Name
PARAMETER
VERSION
CLOCK
CALV
WER
PIR0
PIR1
SCR
EVD
EVM
AR0
AR1
DTR
EVE
IMR
IDR
IER
CR
SR
CV
AT32UC3L016/32/64
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/write
Read-only
Read-only
Read-only
Read-only
Read-only
Write-only
Write-only
Write-only
Write-only
Write-only
Access
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
Reset
-
-
(1)
(1)
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