AT32UC3L032-D3UR Atmel, AT32UC3L032-D3UR Datasheet - Page 731

• Manufacturer Part Number: AT32UC3L032-D3UR
• Description: MCU AVR32 32KB FLASH 48TLLGA
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L032-D3UR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TLLGA
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 7
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: AT32UC3L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 9 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

31.3
31.3.1
31.3.2
31.3.3
32099F–11/2010
On-Chip Debug
Features
Overview
I/O Lines Description
Rev: 2.1.0.0
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Debugging on the AT32UC3L016/32/64 is facilitated by a powerful On-Chip Debug (OCD) sys-
tem. The user accesses this through an external debug tool which connects to the JTAG or
aWire port and the Auxiliary (AUX) port if implemented. The AUX port is primarily used for trace
functions, and an aWire- or JTAG-based debugger is sufficient for basic debugging.
The debug system is based on the Nexus 2.0 standard, class 2+, which includes:
In addition to the mandatory Nexus debug features, the AT32UC3L016/32/64 implements sev-
eral useful OCD features, such as:
The OCD features are controlled by OCD registers, which can be accessed by the debugger, for
instance when the NEXUS_ACCESS JTAG instruction is loaded. The CPU can also access
OCD registers directly using mtdr/mfdr instructions in any privileged mode. The OCD registers
are implemented based on the recommendations in the Nexus 2.0 standard, and are detailed in
the AVR32UC Technical Reference Manual.
The OCD AUX trace port contains a number of pins, as shown in
These are multiplexed with I/O Controller lines, and must explicitly be enabled by writing OCD
registers before the debug session starts. The AUX port is mapped to two different locations,
• Basic run-time control
• Program breakpoints
• Data breakpoints
• Program trace
• Ownership trace
• Data trace
• Debug Communication Channel between CPU and debugger
• Run-time PC monitoring
• CRC checking
• NanoTrace
• Software Quality Assurance (SQA) support
Debug interface in compliance with IEEE-ISTO 5001-2003 (Nexus 2.0) Class 2+
JTAG or aWire access to all on-chip debug functions
Advanced Program, Data, Ownership, and Watchpoint trace supported
NanoTrace aWire- or JTAG-based trace access
Auxiliary port for high-speed trace information
Hardware support for 6 Program and 2 Data breakpoints
Unlimited number of software breakpoints supported
Automatic CRC check of memory regions
AT32UC3L016/32/64
Table 31-6 on page
732.
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