AT32UC3L032-D3UR Atmel, AT32UC3L032-D3UR Datasheet - Page 190

• Manufacturer Part Number: AT32UC3L032-D3UR
• Description: MCU AVR32 32KB FLASH 48TLLGA
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L032-D3UR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TLLGA
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 7
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: AT32UC3L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 9 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

32099F–11/2010
Figure 13-3. DFLL Locking in Closed-Loop
CLK_DFLL is ready to be used when the DFLLn Synchronization Ready bit (DFLLnRDY) in
PCLKSR is set after enabling the DFLL. However, the accuracy of the output frequency depends
on which locks are set.
For lock times, please refere to the Electrical Characteristics chapter.
Drift compensation
The frequency tuner will automatically compensate for drift in the f
locks. If the FINE value overflows or underflows, which should normally not happen, but could
occur due to large drift in temperature and voltage, all locks will be lost, and the COARSE and
FINE values will be recalibrated as described earlier. If any lock is lost the corresponding bit in
PCLKSR will be set, DFLLn Lock Lost on Coarse Value bit (DFLLnLOCKLOSTC) for lock lost on
COARSE value, DFLLn Lock Lost on Fine Value bit (DFLLnLOCKLOSTF) for lock lost on FINE
value and DFLLn Lock Lost on Accurate Value bit (DFLLnLOCKLOSTA) for lock lost on ACCU-
RATE value. The corresponding lock status bit will be cleared when the lock lost bit is set, and
vice versa.
Reference clock stop detection
If CLK_DFLLIF_REF stops or is running at a very slow frequency, the DFLLn Reference Clock
Stopped bit (DFLLnRCS) in PCLKSR will be set. Note that the detection of the clock stop will
take a long time. The DFLLIF operate as if it was in open loop mode if it detects that the refer-
ence clock has stopped. closed-loop mode operation will automatically resume if the
CLK_DFLLIF_REF is restarted.
Frequency error measurement
The ratio between CLK_DFLLIF_REF and CLK_DFLL is measured automatically by the DFLLIF.
The difference between this ratio and DFLLnMUL is stored in the Multiplication Ratio Difference
field (RATIODIFF) in the DFLLn Ratio Register (DFLLnRATIO). The relative error on CLK_DFLL
compared to the target frequency can be calculated as follows:
frequency
frequency
Target
Initial
error
DFLLnLOCKC DFLLnLOCKF DFLLnLOCKA
=
RATIODIFF f
------------------------------------------------ -
2
NUMREF
⋅
AT32UC3L016/32/64
f
DFLL
⋅
REF
DFLL
without losing either of the
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