AT32UC3L032-D3UR Atmel, AT32UC3L032-D3UR Datasheet - Page 280

• Manufacturer Part Number: AT32UC3L032-D3UR
• Description: MCU AVR32 32KB FLASH 48TLLGA
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L032-D3UR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TLLGA
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 7
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: AT32UC3L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 9 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Figure 15-4. Window Mode WDT Timing Diagram
Figure 15-5. Window Mode WDT Timing Diagram, clearing within T
32099F–11/2010
C L R .W D T C L R
W a tc h d o g re s e t
C L R .W D T C L R
W a tch d o g re se t
t= t
t= t
W rite o n e to
W rite o n e to
0
0
The PSEL and Time Ban Prescale Select (TBAN) fields in the CTRL Register selects the WDT
timeout period
where T
bit is not allowed. Doing so will result in a watchdog reset, the device will receive a reset and the
code will start executing form the boot vector, see
will be cleared.
Writing a one to the CLR.WDTCLR bit within the T
counter starts counting from zero (t=t
If the value in the CTRL Register is changed, the WDT counter will be cleared without a watch-
dog reset, regardless of if the value in the WDT counter and the TBAN value.
If the WDT counter reaches T
and the code will start executing form the boot vector.
T
T
tb a n
tb a n
T
timeout
tban
sets the time period when clearing the WDT counter by writing to the CLR.WDTCLR
= T
tban
+ T
psel
= (2
timeout
(TBAN+1)
, the counter will be cleared, the device will receive a reset
0
), entering T
+ 2
(PSEL+1)
tban
, resulting in watchdog reset.
T
T
p s e l
) / f
p se l
tban
psel
Figure 15-5 on page
clk_cnt
, see
period will clear the WDT counter and the
AT32UC3L016/32/64
Figure 15-4 on page
280. The WDT counter
T im e o u t
T im e o u t
280.
280