AT32UC3L032-D3UR Atmel, AT32UC3L032-D3UR Datasheet - Page 395

• Manufacturer Part Number: AT32UC3L032-D3UR
• Description: MCU AVR32 32KB FLASH 48TLLGA
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L032-D3UR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TLLGA
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 7
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: AT32UC3L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 9 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

19.6.8
19.6.8.1
Figure 19-32. Master Node with Peripheral DMA Controller (PDCM=1)
32099F–11/2010
WRITE BUFFER
IDENTIFIER
CHKTYP
CHKDIS
PARDIS
FSDIS
DATA 0
DATA N
NACT
DLC
DLM
|
|
|
|
LIN Frame Handling With The Peripheral DMA Controller
Master Node Configuration
Peripheral DMA
Controller
The USART can be used in association with the Peripheral DMA Controller in order to transfer
data directly into/from the on- and off-chip memories without any processor intervention.
The Peripheral DMA Controller uses the trigger flags, TXRDY and RXRDY, to write or read into
the USART. The Peripheral DMA Controller always writes in the Transmit Holding register (THR)
and it always reads in the Receive Holding register (RHR). The size of the data written or read by
the Peripheral DMA Controller in the USART is always a byte.
The user can choose between two Peripheral DMA Controller modes by the PDCM bit in the LIN
Mode register (LINMR):
The WRITE buffer also contains the Identifier and the DATA, if the USART sends the response
(NACT = PUBLISH).
The READ buffer contains the DATA if the USART receives the response (NACT =
SUBSCRIBE).
• PDCM = 1: the LIN configuration is stored in the WRITE buffer and it is written by the
• PDCM = 0: the LIN configuration is not stored in the WRITE buffer and it must be written by
Peripheral DMA Controller in the Transmit Holding register THR (instead of the LIN Mode
register LINMR). Because the Peripheral DMA Controller transfer size is limited to a byte, the
transfer is split into two accesses. During the first access the bits, NACT, PARDIS, CHKDIS,
CHKTYP, DLM and FSDIS are written. During the second access the 8-bit DLC field is
written.
the user in the LIN Mode register (LINMR).
Peripheral
RXRDY
bus
NODE ACTION = PUBLISH
CONTROLLER
USART LIN
READ BUFFER
IDENTIFIER
WRITE BUFFER
CHKTYP
PARDIS
CHKDIS
FSDIS
NACT
DATA N
DATA 0
DLM
DLC
|
|
|
|
Peripheral DMA
Controller
AT32UC3L016/32/64
Peripheral
RXRDY
TXRDY
bus
NODE ACTION = SUBSCRIBE
CONTROLLER
USART LIN
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