AT32UC3L032-D3UR Atmel, AT32UC3L032-D3UR Datasheet - Page 577

• Manufacturer Part Number: AT32UC3L032-D3UR
• Description: MCU AVR32 32KB FLASH 48TLLGA
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L032-D3UR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TLLGA
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 7
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: AT32UC3L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 9 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

• ACPA: RA Compare Effect on TIOA
• WAVE
• WAVSEL: Waveform Selection
• ENETRG: External Event Trigger Enable
• EEVT: External Event Selection
Note:
• EEVTEDG: External Event Edge Selection
• CPCDIS: Counter Clock Disable with RC Compare
• CPCSTOP: Counter Clock Stopped with RC Compare
32099F–11/2010
EEVTEDG
WAVSEL
ACPA
EEVT
0
1
2
3
0
1
2
3
0
1
2
3
1: Waveform mode is enabled.
0: Waveform mode is disabled (Capture mode is enabled).
1: The external event resets the counter and starts the counter clock.
0: The external event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA
output.
0
1
2
3
1. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms and subse-
1: Counter clock is disabled when counter reaches RC.
0: Counter clock is not disabled when counter reaches RC.
1: Counter clock is stopped when counter reaches RC.
quently no IRQs.
Effect
UP mode without automatic trigger on RC Compare
UPDOWN mode without automatic trigger on RC Compare
UP mode with automatic trigger on RC Compare
UPDOWN mode with automatic trigger on RC Compare
Edge
none
rising edge
falling edge
each edge
Effect
none
set
clear
toggle
Signal selected as external event
TIOB
XC0
XC1
XC2
TIOB Direction
input
output
output
output
(1)
AT32UC3L016/32/64
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