AT32UC3L032-D3UR Atmel, AT32UC3L032-D3UR Datasheet - Page 278

• Manufacturer Part Number: AT32UC3L032-D3UR
• Description: MCU AVR32 32KB FLASH 48TLLGA
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L032-D3UR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TLLGA
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 7
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: AT32UC3L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 9 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

15.5.1.3
15.5.1.4
15.5.1.5
32099F–11/2010
Configuring the WDT
Enabling the WDT
Clearing the WDT Counter
To change the clock for the WDT the following steps need to be taken. Note that the WDT
should always be disabled before changing the CLK_CNT source:
1. Write a zero to the Clock Enable (CEN) bit in the CTRL Register, leaving the other bits as they
are in the CTRL Register. This will stop CLK_CNT.
2. Read back the CTRL Register until the CEN bit reads zero. The clock has now been stopped.
3. Modify the Clock Source Select (CSSEL) bit in the CTRL Register with your new clock selec-
tion and write it to the CTRL Register.
4. Write a one to the CEN bit, leaving the other bits as they are in the CTRL Register. This will
enable the clock.
5. Read back the CTRL Register until the CEN bit reads one. The clock has now been enabled.
If the MODE bit in the CTRL Register is zero, the WDT is in basic mode. The Time Out Prescale
Select (PSEL) field in the CTRL Register selects the WDT timeout period:
To enable the WDT write a one to the Enable (EN) bit in the CTRL Register. Due to internal syn-
chronization, it will take some time for the CTRL.EN bit to read back as one.
The WDT counter is cleared by writing a one to the Watchdog Clear (WDTCLR) bit in the Clear
(CLR) Register, at any correct write to the CTRL Register, or when the counter reaches T
and the chip is reset. In basic mode the CLR.WDTCLR can be written at any time when the WDT
Counter Cleared (CLEARED) bit in the Status Register (SR) is one. Due to internal synchroniza-
tion, clearing the WDT counter takes some time. The SR.CLEARED bit is cleared when writing
to CLR.WDTCLR bit and set when the clearing is done. Any write to the CLR.WDTCLR bit while
SR.CLEARED is zero will be ignored.
Writing to the CLR.WDTCLR bit has to be done in a particular sequence to be valid. The CLR
Register must be written twice, first with the KEY field set to 0x55 and WDTCLR set to one, then
a second write with the KEY set to 0xAA without changing the WDTCLR bit. Writing to the CLR
Register without the correct sequence has no effect.
If the WDT counter is periodically cleared within T
ure 15-2 on page
T
timeout
= T
psel
279.
= 2
(PSEL+1)
/ f
clk_cnt
psel
no watchdog reset will be issued, see
AT32UC3L016/32/64
timeout
Fig-
278