AT32UC3L032-D3UR Atmel, AT32UC3L032-D3UR Datasheet - Page 194

• Manufacturer Part Number: AT32UC3L032-D3UR
• Description: MCU AVR32 32KB FLASH 48TLLGA
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L032-D3UR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TLLGA
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 7
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: AT32UC3L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 9 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

13.5.7
13.5.7.1
13.5.7.2
13.5.7.3
32099F–11/2010
Voltage Regulator (VREG)
Register protection
Controlling voltage regulator output
Factory calibration
gram execution starts in the CPU. If the RCCR.FCD is one then the calibration will not be
changed during a reset. To prevent unexpected writes to RCCR due to software bugs, write
access to this register is protected by a locking mechanism. For details please refer to the
UNLOCK register description.
Although it is not recommended to override default factory settings, it is still possible to override
the default values by writing to RCCR.CALIB.
Rev: 1.0.1.0
The embedded voltage regulator can be used to provide the VDDCORE voltage from VDDIN. It
is controlled by the Voltage Regulator Calibration Register (VREGCR). The voltage regulator is
enabled by default at start-up but can be disabled by software if an external voltage is provided
on the VDDCORE pin. The VREGCR also contains bit to control POR33 detector.
To prevent unexpected writes to VREGCR due to software bugs, write access to this register is
protected by a locking mechanism. For details please refer to the UNLOCK register description.
To prevent further modifications by software, the content of the register can be set as read-only
by writing a one to the Store Final Value bit (VREGCR.SFV). Once this bit is set, software can
not change the VREGCR content until a POR or POR33 reset is applied
The voltage regulator is always enabled at startup, i.e. after a POR33 or an POR reset or when
waking up from SHUTDOWN mode. It can be disabled by software by writing a zero to the
Enable bit (VREGCR.EN). Because of internal synchronization, the voltage regulator is not
immediately enabled or disabled. The actual state of the voltage regulator can be read from the
ON bit (VREGCR.ON).
The voltage regulator output level is controlled by Select VDD field (SELVDD) in VREGCR.
Please refer to the Electrical Characteristic chapter for supported output voltages
After a Power-On-Reset (POR) the VREGCR.CALIB field is loaded with a factory defined value
stored in the Flash fuses.
The Voltage Regulator OK bit (VREGCR.VREGOK) bit indicates when voltage regulator output
has reached its new programmed value
After a Power-On-Reset (POR) the VREGCR.CALIB field is loaded with a factory defined value
stored in the Flash fuses. This value is chosen so that the normal output voltage of the regulator
after a power-up is 1.8V.
Please refer to the Fuse setting chapter for more details about VREG fuses and how to program
the fuses.
Although it is not recommended to override default factory settings, it is still possible to override
these default values by writing to VREGCR.CALIB or altering the values for the VREGIFB flash
fuses.
If the Flash Calibration Done (FCD) bit in the VREGCR is zero at any reset except for POR and
POR33, then the flash calibration will be redone and the VREGCR.FCD bit will be set before pro-
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