AT32UC3L032-D3UR Atmel, AT32UC3L032-D3UR Datasheet - Page 48

• Manufacturer Part Number: AT32UC3L032-D3UR
• Description: MCU AVR32 32KB FLASH 48TLLGA
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L032-D3UR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TLLGA
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 7
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: AT32UC3L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 9 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

7.7.3
Table 7-3.
7.7.4
Table 7-4.
Note:
32099F–11/2010
Offset
0x80C
0x81C
0x82C
Offset
0x800
0x804
0x808
0x810
0x814
0x818
0x820
0x824
0x828
0x830
0x834
1. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter.
Performance Monitor Memory Map
Version Register Memory Map
PDCA Performance Monitor Registers
PDCA Version Register Memory Map
Note:
Performance Control Register
Channel0 Read Max Latency
Channel1 Read Max Latency
Channel0 Write Max Latency
Channel1 Write Max Latency
Channel0 Read Data Cycles
Channel0 Write Data Cycles
Channel1 Read Data Cycles
Channel1 Write Data Cycles
Channel0 Read Stall Cycles
Channel0 Write Stall Cycles
Channel1 Read Stall Cycles
Channel1 Write Stall Cycles
Version Register
1. The number of performance monitors is device specific. If the device has only one perfor-
Register
Register
mance monitor, the Channel1 registers are not available. Please refer to the Module
Configuration section at the end of this chapter for the number of performance monitors on this
device.
(1)
Register Name
Register Name
PCONTROL
PWSTALL0
PWSTALL1
PRSTALL0
PRSTALL1
PWDATA0
PWDATA1
VERSION
PRDATA0
PRDATA1
PWLAT0
PWLAT1
PRLAT0
PRLAT1
AT32UC3L016/32/64
Read/Write
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Access
Access
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
Reset
Reset
-
(1)
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