r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 115

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
7.4.16
Note:
Table 7.4
1. Do not set both the IICTCTWI and IICTCHALF bits to 1 when the I
XCSEL Bit (XCIN/XCOUT pin connect bit)
IOINSEL Bit (I/O port input function select bit)
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
PDi_j bit in PDi register
Address 018Fh
when the SSU function is used.
The XCSEL bit is used to connect XCIN and XCOUT to P4_3 and P4_4, respectively. When this bit is set to 1,
XCIN is connected to P4_3 and XCOUT is connected to P4_4. For how to set XCIN and XCOUT, refer to 9.
Clock Generation Circuit.
The IOINSEL bit is used to select the pin level of an I/O port when the PDi_j (j = 0 to 7) bit in the PDi (i = 0 to
4 or 6) register is set to 1 (output mode). When this bit is set to 1, the I/O port input function reads the pin input
level regardless of the PDi register.
Table 7.4 lists I/O Port Values Read by Using IOINSEL Bit. The IOINSEL bit can be used to change the input
function of all I/O ports except P4_2.
Symbol SDADLY1 SDADLY0 IICTCHALF IICTCTWI IOINSEL
I/O port values read
IICTCHALF I
IICTCTWI I
SDADLY0 SDA digital delay select bit
SDADLY1
IOINSEL
Bit
IOINSEL bit
Symbol
XCSEL
I/O Function Pin Select Register (PINSR)
—
—
I/O Port Values Read by Using IOINSEL Bit
b7
0
XCIN/XCOUT pin connect bit
Reserved bit
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
I/O port input function select bit
bit
2
2
C double transfer rate select
C half transfer rate select bit
(1)
b6
0
Bit Name
b5
0
0
0 (input mode)
Pin input level
(1)
b4
0
0: XCIN not connected to P4_3, XCOUT not
1: XCIN connected to P4_3, XCOUT connected to
Set to 0.
0: The I/O port input function depends on the PDi (i =
1: The I/O port input function reads the pin input level
0: Transfer rate is the same as the value set with bits
1: Transfer rate is twice the value set with bits CKS0
0: Transfer rate is the same as the value set with bits
1: Transfer rate is half the value set with bits CKS0 to
b7 b6
0 0: Digital delay of 3 × f1 cycles
0 1: Digital delay of 11 × f1 cycles
1 0: Digital delay of 19 × f1 cycles
1 1: Do not set.
connected to P4_4
P4_4
0 to 4 or 6) register.
When the PDi_j (j = 0 to 7) bit in the PDi register is
set to 0 (input mode), the pin input level is read.
When the PDi_j bit in the PDi register is set to 1
(output mode), the port latch is read.
regardless of the PDi register.
CKS0 to CKS3 in the ICCR1 register
to CKS3 in the ICCR1 register
CKS0 to CKS3 in the ICCR1 register
CKS3 in the ICCR1 register
b3
0
1
2
C bus function is used. Set these bits to 0
b2
—
0
Port latch value
Function
0
b1
—
0
1 (output mode)
XCSEL
b0
0
Pin input level
Page 83 of 740
1
7. I/O Ports
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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