r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 480

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
Figure 22.8
22.4.1
Table 22.8
i = 0 or 1
Note:
Bit Rate
115200
14400
19200
28800
38400
57600
(bps)
1200
2400
4800
9600
1. For the high-speed on-chip oscillator, the correction value in the FRA4 register should be written into the FRA1
In UART mode, the bit rate is the frequency divided by the UiBRG (i = 0 or 1) register and divided by 16.
register and the correction value in the FRA5 register should be written into the FRA3 register.
This applies when the high-speed on-chip oscillator is selected as the system clock and bits FRA22 to FRA20
in the FRA2 register are set to 000b (divide-by-2 mode). For the precision of the high-speed on-chip oscillator,
refer to 34. Electrical Characteristics .
Source
UiBRG
Count
Bit Rate
f8
f8
f8
f1
f1
f1
f1
f1
f1
f1
Setting value in UiBRG register =
Setting value in UiBRG register =
Formula for Calculating Setting Value in UiBRG (i = 0 or 1) Register
Bit Rate Setting Example in UART Mode (Internal Clock Selected)
UART mode
129 (81h)
129 (81h)
42 (2Ah)
10 (0Ah)
64 (40h)
32 (20h)
86 (56h)
64 (40h)
32 (20h)
21 (15h)
i = 0 or 1
UiBRG
Setting
Value
• Internal clock selected
• External clock selected
System Clock = 20 MHz
Actual Time
113636.36
29069.77
14367.82
19230.77
37878.79
56818.18
(bps)
1201.92
2403.85
4734.85
9615.38
fj: Count source frequency of UiBRG register (f1, f8, f32, or fC)
fEXT: Count source frequency of UiBRG register (external clock)
Setting
Error
(%)
-1.36 29 (1Dh)
-0.22 79 (4Fh)
-1.36 29 (1Dh)
-1.36 19 (13h)
-1.36
0.16 119 (77h)
0.16 59 (3Bh)
0.16 119 (77h)
0.16 59 (3Bh)
0.94 39 (27h)
System Clock = 18.432 MHz
9 (09h)
UiBRG
Setting
Value
Bit Rate × 16
Bit Rate × 16
fEXT
Actual Time
fj
115200.00
14400.00
19200.00
28800.00
38400.00
57600.00
(bps)
1200.00
2400.00
4800.00
9600.00
22. Serial Interface (UARTi (i = 0 or 1))
− 1
− 1
Setting
Error
(%)
0.00 51 (33h)
0.00 25 (19h)
0.00 12 (0Ch)
0.00 51 (33h)
0.00 34 (22h) 14285.71
0.00 25 (19h) 19230.77
0.00 16 (10h)
0.00 12 (0Ch) 38461.54
0.00
0.00
(1)
UiBRG
Setting
8 (08h)
Value
System Clock = 8 MHz
−
55555.56
29411.76
1201.92
2403.85
4807.69
9615.38
Actual
(bps)
Time
Page 448 of 740
−
Setting
Error
(%)
-0.79
-3.55
0.16
0.16
0.16
0.16
0.16
2.12
0.16
−