r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 569

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
26.2.10 IIC bus Status Register (ICSR)
Notes:
1. Each bit is set to 0 by reading 1 before writing 0.
2. This flag is enabled in slave receive mode with the I
3. When two or more master devices attempt to occupy the bus at nearly the same time, if the I
4. The NACKF bit is enabled when the ACKE bit in the ICIER register is set to 1 (when the receive acknowledge bit
5. The RDRF bit is set to 0 when data is read from the ICDRR register.
6. Bits TEND and TDRE are set to 0 when data is written to the ICDRT register.
7. When writing 0 to the ICE bit in the ICCR1 register or 1 to the IICRST bit in the ICCR2 register during an I
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 019Ch
monitors the SDA pin and the data which the I
the bus is occupied by another master.
is set to 1, transfer is halted).
When reading these bits immediately after writing to the ICDRT register, insert three or more NOP instructions
between the instructions used for writing and reading.
interface operation, the BBSY bit in the ICCR2 register and the STOP bit may become undefined. Refer to 26.9
Notes on I
When accessing the ICSR register continuously, insert one or more NOP instructions between the instructions
to access it.
Symbol
Symbol
NACKF No acknowledge
Bit
STOP
RDRF
TEND
TDRE
ADZ
AAS
AL
TDRE
2
C bus Interface .
b7
0
General call address
recognition flag
Slave address
recognition flag
Arbitration lost flag/overrun
error flag
Stop condition detection flag
(1, 7)
detection flag
Receive data register
full flag
Transmit end flag
Transmit data empty flag
TEND
(1, 5)
b6
(1)
0
Bit Name
(1, 4)
(1, 2)
(1)
RDRF
(1, 6)
b5
0
(1, 6)
NACKF
b4
0
This flag is set to 1 when a general call address is
detected.
This flag is set to 1 when the first frame immediately after
the start condition matches bits SVA0 to SVA6 in the SAR
register in slave receive mode (slave address detection
and general call address detection)
I
This flag indicates that arbitration has been lost
in master mode.
This flag is set to 1
Clock synchronous format:
This flag indicates an overrun error.
This flag is set to 1 when:
This flag is set to 1 when a stop condition is detected
after the frame is transferred.
This flag is set to 1 when no ACKnowledge is detected
from the receive device after transmission.
This flag is set to 1 when receive data is transferred from
registers ICDRS to ICDRR.
I
This flag is set to 1 at the rising edge of the 9th clock cycle
of the SCL signal while the TDRE bit is set to 1.
Clock synchronous format:
This flag is set to 1 when the last bit of the transmit frame
is transmitted.
This flag is set to 1 when:
2
2
2
• The internal SDA signal and SDA pin level do not
• The SDA pin is held “H” at start condition detection in
• The last bit of the next unit of data is received
• Data is transferred from registers ICDRT to ICDRS and
• The TRS bit in the ICCR1 register is set to 1 (transmit
• A start condition is generated (including retransmission)
• Slave receive mode is changed to slave transmit mode
C bus format:
C bus format:
C bus Interface transmits is different, the AL flag is set to 1 and
match at the rising edge of the SCL signal in master
transmit mode
master transmit/receive mode
while the RDRF bit is set to 1
the CDRT register is empty
mode)
2
C bus format.
STOP
b3
X
(3)
AL
b2
0
when:
Function
AAS
b1
0
ADZ
b0
0
26. I
2
C bus Interface
Page 537 of 740
2
C bus Interface
2
C bus
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W