r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 529

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
25. Synchronous Serial Communication Unit (SSU)
Synchronous serial communication unit (SSU) supports clock synchronous serial data communication.
25.1
Table 25.1
Note:
Transfer data format
Operating modes
Master/slave device
I/O pins
Transfer clocks
Receive error detection • Overrun error
Multimaster error
detection
Interrupt requests
Selectable functions
Table 25.1 shows a Synchronous Serial Communication Unit Specifications and Figure 25.1 shows a Block
Diagram of Synchronous Serial Communication Unit.
1. Synchronous serial communication unit has only one interrupt vector table.
Overview
Item
Synchronous Serial Communication Unit Specifications
• Transfer data length: 8 to 16 bits
• Clock synchronous communication mode
• 4-wire bus communication mode (including bidirectional communication)
Selectable
SSCK (I/O): Clock I/O pin
SSI (I/O): Data I/O pin
SSO (I/O): Data I/O pin
SCS (I/O): Chip-select I/O pin
• When the MSS bit in the SSCRH register is set to 0 (operates as slave
• When the MSS bit in the SSCRH register is set to 1 (operates as master
• Clock polarity and phase of SSCK can be selected.
• Conflict error
5 interrupt requests (transmit-end, transmit-data-empty, receive-data-full,
overrun error, and conflict error)
• Data transfer direction
• SSCK clock polarity
• SSCK clock phase
device), external clock is selected (input from SSCK pin).
device), internal clock (selectable among f1/256, f1/128, f1/64, f1/32, f1/16,
f1/8 and f1/4, output from SSCK pin) is selected.
Continuous transmission and reception of serial data are supported since
both transmitter and receiver have buffer structures.
Overrun error occurs during reception and completes in error. While the
RDRF bit in the SSSR register is set to 1 (data in the SSRDR register) and
when next serial data receive is completed, the ORER bit is set to 1.
When the SSUMS bit in the SSMR2 register is set to 1 (4-wire bus
communication mode) and the MSS bit in the SSCRH register is set to 1
(operates as master device) and when starting a serial communication, the
CE bit in the SSSR register is set to 1 if “L” applies to the SCS pin input.
When the SSUMS bit in the SSMR2 register is set to 1 (4-wire bus
communication mode), the MSS bit in the SSCRH register is set to 0
(operates as slave device) and the SCS pin input changes state from “L” to
“H”, the CE bit in the SSSR register is set to 1.
Selects MSB-first or LSB-first
Selects “L” or “H” level when clock stops
Selects edge of data change and data download
25. Synchronous Serial Communication Unit (SSU)
(1)
Specification
.
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