r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 661

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
32. Flash Memory
The flash memory can perform in the following three rewrite modes : CPU rewrite mode, standard serial I/O mode, and
parallel I/O mode.
32.1
Table 32.1
Notes:
Table 32.2
Flash memory operating mode
Division of erase blocks
Programming method
Erasure method
Programming and erasure control method
Rewrite control
method
Number of commands
Programming and
erasure endurance
ID code check function
ROM code protection
Function
Rewritable area
Rewrite programs User program
Table 32.1 lists the Flash Memory Version Performance. (Refer to Table 1.1 and Table 1.2 R8C/34M Group
Specifications for items not listed in Table 32.1.)
Flash Memory
Rewrite Mode
1. To perform programming and erasure, use VCC = 2.7 V to 5.5 V as the supply voltage. Do not perform
2. Definition of programming and erasure endurance
3. The number of blocks and block division vary with the MCU. Refer to Figure 32.1 R8C/34M Group Flash
programming and erasure at less than 2.7 V.
The programming and erasure endurance is defined on a per-block basis. If the programming and erasure
endurance is n (n = 1,000 or 10,000), each block can be erased n times. For example, if 1,024 1-byte writes are
performed to different addresses in block A, a 1-Kbyte block, and then the block is erased, the programming/
erasure endurance still stands at one. When performing 100 or more rewrites, the actual erase count can be
reduced by executing program operations in such a way that all blank areas are used before performing an
erase operation. Avoid rewriting only particular blocks and try to average out the programming and erasure
endurance of the blocks. It is also advisable to retain data on the erasure endurance of each block and limit the
number of erase operations to a certain number.
Memory Block Diagram for details.
Overview
Flash Memory Version Performance
Flash Memory Rewrite Mode
(2)
User ROM area is rewritten by
executing software commands
from the CPU.
User ROM
Item
Blocks 0 to 3
(Program ROM)
Blocks A, B, C, and D
(Data flash)
Blocks 0 to 3
(Program ROM)
Blocks A, B, C, and D
(Data flash)
CPU Rewrite Mode
(3)
(3)
(1)
Refer to Figure 32.1 .
3 modes (CPU rewrite, standard serial I/O, and parallel I/O)
Byte units
Block erase
Program and erase control by software commands
Rewrite protect control in block units by the lock bit
Individual rewrite protect control on blocks A, B, C, and D
by bits FMR14, FMR15, FMR16, and FMR17 in the FMR1 register
7 commands
1,000 times
10,000 times
Standard serial I/O mode supported
Parallel I/O mode supported
Standard boot program
User ROM area is rewritten
using a dedicated serial
programmer.
User ROM
Standard Serial I/O Mode
Specification
User ROM area is rewritten
using a dedicated parallel
programmer.
User ROM
–
Parallel I/O Mode
32. Flash Memory
Page 629 of 740