r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 311

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
Figure 19.10
19.5.5
The above applies under the following conditions:
• Bits BFC and BFD in the TRCMR register are set to 0 (TRCGRC and TRCGRD do not operate as buffers).
• Bits EA, EB, and EC in the TRCOER register are set to 0 (output from TRCIOA, TRCIOB, and TRCIOC enabled).
• The CCLR bit in the TRCCR1 register is set to 1 (set the TRC register to 0000h by TRCGRA compare match).
• In the TRCCR1 register, bits TOA and TOB are set to 0 (“L” initial output until compare match) and the TOC bit is set to 1 (“H” initial output until
• Bits IOA2 to IOA0 in the TRCIOR0 register are set to 011b (TRCIOA output inverted at TRCGRA compare match).
• Bits IOB2 to IOB0 in the TRCIOR0 register are set to 010b (“H” TRCIOB output at TRCGRB compare match).
• Bits IOC2 to IOC2 in the TRCIOR1 register are set to 001b (“L” TRCIOC output at TRCGRC compare match).
• The CSEL bit in the TRCCR2 register is set to 0 (TRC count continues after TRCGRA compare match).
compare match).
TRCMR register
TRCSR register
TRCSR register
TRCSR register
TRCIOA output
TRCIOB output
TRCIOC output
Count source
TSTART bit in
Operating Example
IMFA bit in
IMFB bit in
IMFC bit in
TRC register value
Operating Example of Output Compare Function
m
n
p
Initial output “H”
Initial output “L”
Initial output “L”
P+1
n+1
m+1
“L” output by compare match
Set to 0 by a program
compare match
“H” output by
Set to 0 by a program
m: TRCGRA register setting value
n: TRCGRB register setting value
p: TRCGRC register setting value
Output inverted by
compare match
Set to 0 by a program
m+1
Output level held
Output level held
Output level held
Count
stops
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restarts
Count
19. Timer RC