r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 313
r5f21346mnfp
Manufacturer Part Number
r5f21346mnfp
Description
Single-chip Mcus Incorporates The R8c Cpu Core
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R5F21346MNFP.pdf
(776 pages)
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R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
Figure 19.12
The above applies under the following conditions:
• Bits BFC and BFD in the TRCMR register are set to 0 (registers TRCGRC and TRCGRD are not used as buffer register).
• Bits EA and EB in the TRCOER register are set to 0 (enable TRCIOA and TRCIOB pin outputs).
• The CCLR bit in the TRCCR1 register are set to 1 (set the TRC register to 0000h by compare match in the TRCGRA register).
• Bits TOA and TOB in the TRCCR1 register are set to 0 (initial output “L” to compare match).
• Bits IOA2 to IOA0 in the TRCIOR0 register are set to 011b (TRCIOA output inverted at TRCGRA register compare match).
• Bits IOB2 to IOB0 in the TRCIOR0 register are set to 011b (TRCIOB output inverted at TRCGRB register compare match).
• Bits IOC2 to IOC0 in the TRCIOR1 register are set to 011b (TRCIOA output inverted at TRCGRC register compare match).
• The IOC3 bit in the TRCIOR1 register are set to 0 (TRCIOA output register).
• Bits IOD2 to IOD0 in the TRCIOR1 register are set to 011b (TRCIOB output inverted at TRCGRD register compare match).
• The IOD3 bit in the TRCIOR1 register are set to 0 (TRCIOB output register).
• The CSEL bit in the TRCCR2 register are set to 0 (TRC continues counting after compare match).
TRCSR register
TRCSR register
TRCSR register
TRCSR register
TRCIOA output
TRCIOB output
Count source
IMFA bit in
IMFC bit in
IMFB bit in
IMFD bit in
Value in TRC register
FFFFh
Pin and TRCGRD Register is Used for Output Control of TRCIOB Pin
Operating Example When TRCGRC Register is Used for Output Control of TRCIOA
0000h
Initial output “L”
Initial output “L”
m
n
p
q
Output inverted by compare match
Set to 0 by a program
Output inverted by compare match
Set to 0 by a program
q+1
p+1
n+1
p-q
m+1
Set to 0 by a program
m: Value set in TRCGRA register
n: Value set in TRCGRC register
p: Value set in TRCGRB register
q: Value set in TRCGRD register
Set to 0 by a program
m-n
Page 281 of 740
19. Timer RC
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