r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 507

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
Figure 23.10
Figure 23.11
23.4.4
23.4.5
The data written to the U2TB register has its logic inverted before being transmitted. Similarly, the received
data has its logic inverted when read from the U2RB register. Figure 23.10 shows the Serial Data Logic
Switching.
This function inverts the polarities of the TXD2 pin output and RXD2 pin input. The logic levels of all I/O data
(including bits for start, stop, and parity) are inverted. Figure 23.11 shows the TXD and RXD I/O Inversion.
(1) U2LCH bit in U2C1 Register = 0 (not inverted)
(2) U2LCH Bit in U2C1 Register = 1 (inverted)
The above applies when:
• CKPOL bit in U2C0 register = 0 (transmit data output at the falling edge of the transfer clock)
• UFORM bit in U2C0 register = 0 (LSB first)
• STPS bit in U2MR register = 0 (one stop bit)
• PRYE bit in U2MR register = 1 (parity enabled)
Transfer clock
TXD2
(not inverted)
Transfer clock
TXD2
(inverted)
Serial Data Logic Switching Function
TXD and RXD I/O Polarity Inverse Function
(1) IOPOL Bit in U2MR Register = 0 (not inverted)
(2) IOPOL Bit in U2MR Register = 1 (inverted)
The above applies when:
Serial Data Logic Switching
TXD and RXD I/O Inversion
Transfer clock
TXD2
(not inverted)
RXD2
(not inverted)
Transfer clock
TXD2
(inverted)
RXD2
(inverted)
• UFORM bit in U2C0 register = 0 (LSB first)
• STPS bit in U2MR register = 0 (one stop bit)
• PRYE bit in U2MR register = 1 (parity enabled)
ST
ST
D0
D0
ST
ST
ST
ST
D1
D1
D0
D0
D0
D0
D2
D2
D1
D1
D1
D1
D3
D3
D2
D2
D2
D2
D4
D4
D3
D3
D3
D3
D5
D5
D4
D4
D4
D4
D6
D6
D5
D5
D5
D5
ST: Start bit
P: Parity bit
SP: Stop bit
D7
D7
D6
D6
D6
D6
D7
D7
D7
D7
P
P
SP
SP
P
P
P
P
23. Serial Interface (UART2)
ST: Start bit
P: Parity bit
SP: Stop bit
SP
SP
SP
SP
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