r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 465

no-image

r5f21346mnfp

Manufacturer Part Number
r5f21346mnfp
Description
Single-chip Mcus Incorporates The R8c Cpu Core
Manufacturer
Renesas Electronics Corporation.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
r5f21346mnfp#V0
Manufacturer:
Renesas Electronics America
Quantity:
10 000
R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
22.2.4
Note:
22.2.5
Notes:
1. If the BRG count source is switched, set the UiBRG register again.
1. The RI bit is set to 0 when the higher byte of the UiRB register is read.
2. In UART mode, set the UiRRM bit to 0 (continuous receive mode disabled).
After Reset
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 00A4h (U0C0), 0164h (U1C0)
Address 00A5h (U0C1), 0165h (U1C1)
Symbol UFORM
Symbol
UFORM Transfer format select bit
Symbol
CKPOL CLK polarity select bit
Symbol
TXEPT
UiRRM
Bit
Bit
UiIRS
CLK0
CLK1
NCH
UARTi Transmit/Receive Control Register 0 (UiC0) (i = 0 or 1)
UARTi Transmit/Receive Control Register 1 (UiC1) (i = 0 or 1)
RE
TE
RI
TI
b7
b7
0
0
BRG count source select bit
Reserved bit
Transmit register empty flag
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
Data output select bit
Transmit enable bit
Transmit buffer empty flag
Receive enable bit
Receive complete flag
UARTi transmit interrupt source
select bit
UARTi continuous receive mode
enable bit
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
CKPOL
b6
b6
0
0
(2)
Bit Name
Bit Name
UiRRM
NCH
b5
b5
0
0
(1)
(1)
UiIRS
b4
b4
0
0
b1 b0
Set to 0.
0: Data present in the transmit register
1: No data in the transmit register
0: TXDi pin set to CMOS output
1: TXDi pin set to N-channel open-drain output
0: Transmit data output at the falling edge and receive
1: Transmit data output at the rising edge and receive
0: LSB first
1: MSB first
0 0: f1 selected
0 1: f8 selected
1 0: f32 selected
1 1: fC selected
(transmission in progress)
(transmission completed)
data input at the rising edge of the transfer clock
data input at the falling edge of the transfer clock
0: Transmission disabled
1: Transmission enabled
0: Data present in the UiTB register
1: No data in the UiTB register
0: Reception disabled
1: Reception enabled
0: No data in the UiRB register
1: Data present in the UiRB register
0: Transmission buffer empty (TI = 1)
1: Transmission completed (TXEPT = 1)
0: Continuous receive mode disabled
1: Continuous receive mode enabled
TXEPT
b3
b3
RI
1
0
RE
b2
b2
0
0
22. Serial Interface (UARTi (i = 0 or 1))
Function
Function
CLK1
b1
b1
TI
0
1
CLK0
TE
b0
b0
0
0
Page 433 of 740
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R

Related parts for r5f21346mnfp