r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 541
r5f21346mnfp
Manufacturer Part Number
r5f21346mnfp
Description
Single-chip Mcus Incorporates The R8c Cpu Core
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R5F21346MNFP.pdf
(776 pages)
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R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
Figure 25.3
25.3.2
• SSUMS = 0
• SSUMS = 1 (4-wire bus communication mode),
25.3.2.1
(clock synchronous communication mode)
BIDE = 0 (standard mode), and MSS = 0 (operates
as slave device)
The SSTRSR register is a shift register for transmitting and receiving serial data.
When transmit data is transferred from the SSTDR register to the SSTRSR register and the MLS bit in the
SSMR register is set to 0 (MSB-first), the bit 0 in the SSTDR register is transferred to bit 0 in the SSTRSR
register. When the MLS bit is set to 1 (LSB-first), bit 7 in the SSTDR register is transferred to bit 0 in the
SSTRSR register.
The connection between the data I/O pins and SSTRSR register (SS shift register) changes according to a
combination of the MSS bit in the SSCRH register and the SSUMS bit in the SSMR2 register. The connection
also changes according to the BIDE bit in the SSMR2 register.
Figure 25.3 shows the Association between Data I/O Pins and SSTRSR Register.
SSTRSR register
SSTRSR register
SS Shift Register (SSTRSR)
Association between Data I/O Pins and SS Shift Register
Association between Data I/O Pins and SSTRSR Register
SSO
SSI
SSO
SSI
• SSUMS = 1 (4-wire bus communication mode),
• SSUMS = 1 (4-wire bus communication mode) and
BIDE = 0 (standard mode), and MSS = 1 (operates as
master device)
BIDE = 1 (bidirectional mode)
25. Synchronous Serial Communication Unit (SSU)
SSTRSR register
SSTRSR register
Page 509 of 740
SSO
SSI
SSO
SSI
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