r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 252

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
17.5
Table 17.4
Note:
Count source
Count operations
Divide ratio
Count start condition
Count stop conditions • 0 (count stops) is written to the TSTART bit in the TRACR register.
Interrupt request
generation timing
TRAIO pin function
TRAO pin function
Read from timer
Write to timer
Selectable functions
In event counter mode, external signal inputs to the TRAIO pin are counted (refer to Table 17.4 Event Counter
Mode Specifications).
1. The level of the output pulse becomes the level when the pulse output starts when the TRAMR
register is written to.
Event Counter Mode
Item
Event Counter Mode Specifications
External signal which is input to TRAIO pin (active edge selectable by a program)
• Decrement
• When the timer underflows, the contents of the reload register are reloaded and
1/(n+1)(m+1)
n: setting value of TRAPRE register, m: setting value of TRA register
1 (count starts) is written to the TSTART bit in the TRACR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register.
When timer RA underflows [timer RA interrupt].
Count source input
Programmable I/O port or pulse output
The count value can be read by reading registers TRA and TRAPRE.
• When registers TRAPRE and TRA are written while the count is stopped, values
• When registers TRAPRE and TRA are written during the count, values are
• TRAIO input polarity switch function
• Count source input pin select function
• Pulse output function
• TRAO pin select function
• Digital filter function
• Event input control function
the count is continued.
are written to both the reload register and counter.
written to the reload register and counter (refer to 17.3.2 Timer Write Control
during Count Operation ).
The active edge of the count source is selected by the TEDGSEL bit in the
TRAIOC register.
P1_5 or P1_7 is selected by bits TRAIOSEL0 to TRAIOSEL1 in the TRASR
register.
Pulses of inverted polarity can be output from the TRAO pin each time the timer
underflows (selectable by the TOENA bit in the TRAIOC register).
P3_0 or P3_7 is selected by the TRAOSEL0 bit in the TRASR register.
Whether enabling or disabling the digital filter and the sampling frequency is
selected by bits TIPF0 and TIPF1 in the TRAIOC register.
The enabled period for the event input to the TRAIO pin is selected by bits
TIOGT0 and TIOGT1 in the TRAIOC register.
Specification
(1)
(1)
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17. Timer RA