r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 501

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
23.4
Table 23.5
Notes:
Transfer data format
Transfer clock
Transmit/receive control
Transmit start conditions
Receive start conditions
Interrupt request generation
timing
Error detection
Selectable functions
In UART mode, data is transmitted and received after setting the desired bit rate and transfer data format. Table
23.5 lists the UART Mode Specifications. Table 23.6 lists the Registers Used and Settings in UART Mode.
1. If an overrun error occurs, the receive data in the U2RB register will be undefined.
2. The framing error flag and the parity error flag are set to 1 when data is transferred from the UART2 receive
register to the U2RB register.
Clock Asynchronous Serial I/O (UART) Mode
Item
UART Mode Specifications
• Character bits (transfer data): Selectable from 7, 8, or 9 bits
• Start bit:1 bit
• Parity bit: Selectable from odd, even, or none
• Stop bits: Selectable from 1 bit or 2 bits
• The CKDIR bit in the U2MR register is set to 0 (internal clock): fj/(16(n + 1))
• The CKDIR bit is set to 1 (external clock): fEXT/(16(n + 1))
Selectable from the CTS function, RTS function, or CTS/RTS function disabled.
To start transmission, the following requirements must be met:
• The TE bit in the U2C1 register is set to 1 (transmission enabled).
• The TI bit in the U2C1 register is set to 0 (data present in the U2TB register).
• If the CTS function is selected, input to the CTS2 pin = “L”.
To start reception, the following requirements must be met:
• The RE bit in the U2C1 register is set to 1 (reception enabled).
• Start bit detection
For transmission, one of the following conditions can be selected.
• The U2IRS bit in the U2C1 register is set to 0 (transmit buffer empty):
• The U2IRS bit is set to 1 (transmission completed):
For reception
• When data is transferred from the UART2 receive register to the U2RB register
• Overrun error
• Framing error
• Parity error
• Error sum flag
• LSB first, MSB first selection
• Serial data logic switching
• TXD, RXD I/O polarity switching
• RXD2 digital filter selection
fEXT: Input from CLK2 pin n: Setting value in the U2BRG register: 00h to FFh
When data is transferred from the U2TB register to the UART2 transmit register
(at start of transmission).
When data transmission from the UART2 transmit register is completed.
(at completion of reception).
This error occurs if the serial interface starts receiving the next unit of data before
reading the U2RB register and receives the bit one before the last stop bit of the
next unit of data.
This error occurs when the set number of stop bits is not detected.
This error occurs when if parity is enabled, the number of 1’s in the parity and
character bits does not match the set number of 1’s.
This flag is set to 1 if an overrun, framing, or parity error occurs.
Whether transmitting or receiving data begins with bit 0 or begins with bit 7 can be
selected.
This function inverts the logic of the transmit/receive data. The start and stop bits
are not inverted.
This function inverts the polarities of the TXD pin output and RXD pin input. The
logic levels of all I/O data are inverted.
The RXD2 input signal can be enabled or disabled.
fj = f1, f8, f32, fC n = setting value in the U2BRG register: 00h to FFh
(2)
(1)
(2)
Specification
23. Serial Interface (UART2)
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