r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 742

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
35.7
35.7.1
35.7.2
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Timer RB stops counting after a reset. Set the values in the timer RB and timer RB prescalers before the count
starts.
Even if the prescaler and timer RB is read out in 16-bit units, these registers are read 1 byte at a time by the MCU.
Consequently, the timer value may be updated during the period when these two registers are being read.
In programmable one-shot generation mode and programmable wait one-shot generation mode, when setting the
TSTART bit in the TRBCR register to 0 (stops counting) or setting the TOSSP bit in the TRBOCR register to 1
(stops one-shot), the timer reloads the value of reload register and stops. Therefore, in programmable one-shot
generation mode and programmable wait one-shot generation mode, read the timer count value before the timer
stops.
The TCSTF bit remains 0 (count stops) for 1 to 2 cycles of the count source after setting the TSTART bit to 1
(count starts) while the count is stopped.
During this time, do not access registers associated with timer RB
counting at the first valid edge of the count source after the TCSTF bit is set to 1 (during count).
The TCSTF bit remains 1 for 1 to 2 cycles of the count source after setting the TSTART bit to 0 (count stops)
while the count is in progress. Timer RB counting is stopped when the TCSTF bit is set to 0.
During this time, do not access registers associated with timer RB
Note:
If the TSTOP bit in the TRBCR register is set to 1 during timer operation, timer RB stops immediately.
If 1 is written to the TOSST or TOSSP bit in the TRBOCR register, the value of the TOSSTF bit changes after
one or two cycles of the count source have elapsed. If the TOSSP bit is written to 1 during the period between
when the TOSST bit is written to 1 and when the TOSSTF bit is set to 1, the TOSSTF bit may be set to either 0 or
1 depending on the content state. Likewise, if the TOSST bit is written to 1 during the period between when the
TOSSP bit is written to 1 and when the TOSSTF bit is set to 0, the TOSSTF bit may be set to either 0 or 1.
To use the underflow signal of timer RA as the count source for timer RB, set timer RA in timer mode, pulse
output mode, or event count mode.
To write to registers TRBPRE and TRBPR during count operation (TCSTF bit in the TRBCR register is set to
1), note the following points:
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To write to registers TRBPRE and TRBPR during count operation (TCSTF bit in the TRBCR register is set to
1), note the following points:
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1. Registers associated with timer RB: TRBCR, TRBOCR, TRBIOC, TRBMR, TRBPRE, TRBSC, and
When the TRBPRE register is written continuously, allow three or more cycles of the count source for each
write interval.
When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow for
each write interval.
When the TRBPRE register is written continuously, allow three or more cycles of the count source for each
write interval.
When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow for
each write interval.
Notes on Timer RB
TRBPR.
Timer Mode
Programmable Waveform Generation Mode
(1)
(1)
other than the TCSTF bit.
other than the TCSTF bit. Timer RB starts
35. Usage Notes
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