r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 526

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
23.7
23.7.1
23.7.1.1
23.7.1.2
23.7.1.3
When the RTS function is used with an external clock, the RTS2 pin outputs “L,” which informs the
transmitting side that the MCU is ready for a receive operation. The RTS2 pin outputs “H” when a receive
operation starts. Therefore, the transmit timing and receive timing can be synchronized by connecting the RTS2
pin to the CTS2 pin of the transmitting side. The RTS function is disabled when an internal clock is selected.
If an external clock is selected, the following conditions must be met while the external clock is held high when
the CKPOL bit in the U2C0 register is set to 0 (transmit data output at the falling edge and receive data input at
the rising edge of the transfer clock), or while the external clock is held low when the CKPOL bit is set to 1
(transmit data output at the rising edge and receive data input at the falling edge of the transfer clock).
• The TE bit in the U2C1 register = 1 (transmission enabled)
• The TI bit in the U2C1 register = 0 (data present in the U2TB register)
• If the CTS function is selected, input on the CTS2 pin = “L”
In clock synchronous serial I/O mode, the shift clock is generated by activating the transmitter. Set the UART2-
associated registers for transmit operation even if the MCU is used for receive operation only. Dummy data is
output from the TXD2 pin while receiving.
When an internal clock is selected, the shift clock is generated by setting the TE bit in the U2C1 register to 1
(transmission enabled) and placing dummy data in the U2TB register. When an external clock is selected, set
the TE bit to 1 (transmission enabled), place dummy data in the U2TB register, and input an external clock to
the CLK2 pin to generate the shift clock.
If data is received consecutively, an overrun error occurs when the RE bit in the U2C1 register is set to 1 (data
present in the U2RB register) and the next receive data is received in the UART2 receive register. Then, the
OER bit in the U2RB register is set to 1 (overrun error). At this time, the U2RB register value is undefined. If an
overrun error occurs, the IR bit in the S2RIC register remains unchanged.
To receive data consecutively, set dummy data in the low-order byte in the U2TB register per each receive
operation.
If an external clock is selected, the following conditions must be met while the external clock is held high when
the CKPOL bit is set to 0, or while the external clock is held low when the CKPOL bit is set to 1.
• The RE bit in the U2C1 register = 1 (reception enabled)
• The TE bit in the U2C1 register = 1 (transmission enabled)
• The TI bit in the U2C1 register = 0 (data present in the U2TB register)
Notes on Serial Interface (UART2)
Clock Synchronous Serial I/O Mode
Transmission/Reception
Transmission
Reception
23. Serial Interface (UART2)
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