r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 165

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
Figure 9.6
FMR0 Register
(flash memory
(flash memory
9.7.2.7
FMSTP Bit
operates)
stops)
Figure 9.6 shows the Time from Wait Mode to Interrupt Routine Execution after WAIT instruction is Executed.
To use a peripheral function interrupt to exit wait mode, set up the following before executing the WAIT
instruction.
(1) Set the interrupt priority level in bits ILVL2 to ILVL0 of the peripheral function interrupts to be used for
(2) Set the I flag to 1.
(3) Operate the peripheral function to be used for exiting stop mode.
When the MCU exits by a peripheral function interrupt, the time (number of cycles) between interrupt request
generation and interrupt routine execution is determined by the settings of the FMSTP bit in the FMR0 register
and the VCA20 bit in the VCA2 register, as shown in Figure 9.6.
The clock set by bits CM35, CM36, and CM37 in the CM3 register is used as the CPU clock when the MCU
exits wait mode by a peripheral function interrupt. At this time, the CM06 bit in the CM0 register and bits
CM16 and CM17 in the CM1 register automatically change.
0
1
exiting stop mode. Set bits ILVL2 to ILVL0 of the peripheral function interrupts that are not to be used for
exiting stop mode to 000b (interrupt disabled).
low consumption disabled)
low consumption enabled)
low consumption enabled)
low consumption disabled
Exiting Wait Mode after WAIT Instruction is Executed
Time from Wait Mode to Interrupt Routine Execution after WAIT instruction is
Executed
VCA2 Register
(internal power
(internal power
(internal power
(internal power
Wait mode
VCA20 Bit
0
1
0
1
Interrupt request generation
stabilization time
Stabilization Time
Internal power
100 µs (max.)
Internal Power
100 µs (max.)
100 µs (max.)
T0
0 µs
0 µs
(T0)
Period of system clock
Period of system clock
activation sequence
× 1 cycle + 60 µs
Activation (T1)
Flash memory
Flash Memory
Time until
× 1 cycle
(max.)
T1
Period of CPU clock
Same as above
restart sequence
Supply (T2)
CPU Clock
× 2 cycles
Time until
CPU clock
T2
Period of CPU clock
Interrupt sequence
Same as above
Sequence (T3)
× 20 cycles
9. Clock Generation Circuit
Time for
Interrupt
T3
The total of T0
to T3 is the time
from wait mode to
interrupt routine
execution.
Page 133 of 740
Remarks