SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 226

• Manufacturer Part Number: SAM4S16C
• Manufacturer: Atmel Corporation

Specifications of SAM4S16C

• Flash (kbytes): 1024 Kbytes
• Pin Count: 100
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 79
• Ext Interrupts: 79
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

This fault is chained to the handler. This means that when this bit is 1, the original return stack is still present. The proces-
sor has not adjusted the SP from the failing return, and has not performed a new save. The processor has not written a
fault address to the SCB_MMFAR register.
• MSTKERR: Memory Manager Fault on Stacking for Exception Entry
This is part of
0: No stacking fault.
1: Stacking for an exception entry has caused one or more access violations.
When this bit is 1, the SP is still adjusted but the values in the context area on the stack might be incorrect. The processor
has not written a fault address to SCB_MMFAR register.
• MLSPERR: MemManage during Lazy State Preservation
This is part of
0: No MemManage fault occurred during the floating-point lazy state preservation.
1: A MemManage fault occurred during the floating-point lazy state preservation.
• MMARVALID: Memory Management Fault Address Register (SCB_MMFAR) Valid Flag
This is part of
0: The value in SCB_MMFAR is not a valid fault address.
1: SCB_MMFAR register holds a valid fault address.
If a memory management fault occurs and is escalated to a hard fault because of priority, the hard fault handler must set
this bit to 0. This prevents problems on return to a stacked active memory management fault handler whose SCB_MMFAR
value has been overwritten.
• IBUSERR: Instruction Bus Error
This is part of
0: No instruction bus error.
1: Instruction bus error.
The processor detects the instruction bus error on prefetching an instruction, but it sets the IBUSERR flag to 1 only if it
attempts to issue the faulting instruction.
When the processor sets this bit to 1, it does not write a fault address to the BFAR register.
• PRECISERR: Precise Data Bus Error
This is part of
0: No precise data bus error.
1: A data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the
fault.
When the processor sets this bit to 1, it writes the faulting address to the SCB_BFAR register.
• IMPRECISERR: Imprecise Data Bus Error
This is part of
0: No imprecise data bus error.
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SAM4S
SAM4S
“MMFSR: Memory Management Fault Status Subregister”
“MMFSR: Memory Management Fault Status Subregister”
“MMFSR: Memory Management Fault Status Subregister”
“BFSR: Bus Fault Status Subregister”
“BFSR: Bus Fault Status Subregister”
“BFSR: Bus Fault Status Subregister”
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11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11