SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 263
SAM4S16C
Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Specifications of SAM4S16C
Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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12.5.6.2
12.5.6.3
12.5.7
12.5.7.1
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
IEEE
Asynchronous Mode
5.4.3. How to Configure the TPIU
JTAG Boundary-scan Register
®
1149.1 JTAG Boundary Scan
The TPIU is configured in asynchronous mode, trace data are output using the single TRAC-
ESWO pin. The TRACESWO signal is multiplexed with the TDO signal of the JTAG Debug Port.
As a consequence, asynchronous trace mode is only available when the Serial Wire Debug
mode is selected since TDO signal is used in JTAG debug mode.
Two encoding formats are available for the single pin output:
This example only concerns the asynchronous trace mode.
IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging
technology.
IEEE 1149.1 JTAG Boundary Scan is enabled when TST is tied to low, while JTAGSEL is high
during power-up, and must be kept in this state during the whole boundary scan operation. The
SAMPLE, EXTEST and BYPASS functions are implemented. In SWD/JTAG debug mode, the
ARM processor responds with a non-JTAG chip ID that identifies the processor. This is not IEEE
1149.1 JTAG-compliant.
It is not possible to switch directly between JTAG Boundary Scan and SWJ Debug Port opera-
tions. A chip reset must be performed after JTAGSEL is changed.
A Boundary-scan Descriptor Language (BSDL) file is provided on
test.
The Boundary-scan Register (BSR) contains a number of bits which correspond to active pins
and associated control signals.
Each SAM4 input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit con-
tains data that can be forced on the pad. The INPUT bit facilitates the observability of data
applied to the pad. The CONTROL bit selects the direction of the pad.
For more information, please refer to BDSL files available for the SAM4 Series.
• Manchester encoded stream. This is the reset value.
• NRZ_based UART byte structure
• Set the TRCENA bit to 1 into the Debug Exception and Monitor Register (0xE000EDFC) to
• Write 0x2 into the Selected Pin Protocol Register
• Write 0x100 into the Formatter and Flush Control Register
• Set the suitable clock prescaler value into the Async Clock Prescaler Register to scale the
enable the use of trace and debug blocks.
baud rate of the asynchronous output (this can be done automatically by the debugging tool).
– Select the Serial Wire Output – NRZ
Atmel’s web site
SAM4S
SAM4S
to set up the
263
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